[PATCH] D50667: [ARM] Make PerformSHLSimplify add nodes to the DAG worklist correctly.

[Eli Friedman via Phabricator via llvm-commits]

efriedma created this revision.
efriedma added reviewers: samparker, mstorsjo, john.brawn.
Herald added a reviewer: javed.absar.
Herald added subscribers: chrib, kristof.beyls.

Intentionally excluding nodes from the DAGCombine worklist is likely to lead to weird optimizations and infinite loops, so it's generally a bad idea.

To avoid the infinite loops, fix DAGCombine to use the isDesirableToCommuteWithShift target hook before performing the transforms in question, and implement the target hook in the ARM backend disable the transforms in question.

Fixes https://bugs.llvm.org/show_bug.cgi?id=38530 . (I don't have a reduced testcase for that bug. But we should have sufficient test coverage for PerformSHLSimplify given that we're not playing weird tricks with the worklist.  I can try to bugpoint it if necessary, though.)


Repository:
  rL LLVM

https://reviews.llvm.org/D50667

Files:
  include/llvm/CodeGen/TargetLowering.h
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/Target/AArch64/AArch64ISelLowering.cpp
  lib/Target/AArch64/AArch64ISelLowering.h
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMISelLowering.h

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D50667.160450.patch
Type: text/x-patch
Size: 4980 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180813/ac109480/attachment.bin>