[PATCH] D50070: [X86] Improved sched models for X86 CMPXCHG* instructions

[Andrew V. Tischenko via Phabricator via llvm-commits]

avt77 updated this revision to Diff 160325.
avt77 added a comment.
Herald added a subscriber: gbedwell.
Herald added a reviewer: andreadb.

The code was re-based. We have 2 changed tests for SandyBridge (Generic). I did not find the proper numbers in Intel SDMs or on Agner site that's why I don't know what's beter the new results or the old ones. The old sched model does not use SBPort4 for memory ops and that looks strange for me. Could anyone help me with these tests?


https://reviews.llvm.org/D50070

Files:
  lib/Target/X86/X86InstrInfo.td
  lib/Target/X86/X86SchedBroadwell.td
  lib/Target/X86/X86SchedHaswell.td
  lib/Target/X86/X86SchedSandyBridge.td
  lib/Target/X86/X86SchedSkylakeClient.td
  lib/Target/X86/X86SchedSkylakeServer.td
  lib/Target/X86/X86Schedule.td
  lib/Target/X86/X86ScheduleAtom.td
  lib/Target/X86/X86ScheduleBtVer2.td
  lib/Target/X86/X86ScheduleSLM.td
  lib/Target/X86/X86ScheduleZnver1.td
  test/tools/llvm-mca/X86/Generic/resources-cmpxchg.s
  test/tools/llvm-mca/X86/Generic/resources-x86_64.s
  test/tools/llvm-mca/X86/SandyBridge/resources-cmpxchg.s
  test/tools/llvm-mca/X86/SandyBridge/resources-x86_64.s

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