[llvm] r339546 - [ARM] Added FP16 VREV Vector Instrinsic CodeGen support

[Luke Geeson via llvm-commits]

Author: lukegeeson
Date: Mon Aug 13 01:37:41 2018
New Revision: 339546

URL: http://llvm.org/viewvc/llvm-project?rev=339546&view=rev
Log:
[ARM] Added FP16 VREV Vector Instrinsic CodeGen support

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
    llvm/trunk/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll

Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=339546&r1=339545&r2=339546&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Aug 13 01:37:41 2018
@@ -6589,6 +6589,8 @@ def VREV64q8  : VREV64Q<0b00, "vrev64",
 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
+def : Pat<(v8f16 (NEONvrev64 (v8f16 QPR:$Vm))), (VREV64q16 QPR:$Vm)>;
+def : Pat<(v4f16 (NEONvrev64 (v4f16 DPR:$Vm))), (VREV64d16 DPR:$Vm)>;
 
 //   VREV32   : Vector Reverse elements within 32-bit words
 

Modified: llvm/trunk/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll?rev=339546&r1=339545&r2=339546&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll Mon Aug 13 01:37:41 2018
@@ -1213,19 +1213,17 @@ entry:
   ret <8 x half> %vext
 }
 
-; FIXME (PR38404)
-;
-;define dso_local <4 x half> @test_vrev64_f16(<4 x half> %a) {
-;entry:
-;  %shuffle.i = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
-;  ret <4 x half> %shuffle.i
-;}
-;
-;define dso_local <8 x half> @test_vrev64q_f16(<8 x half> %a) {
-;entry:
-;  %shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
-;  ret <8 x half> %shuffle.i
-;}
+define dso_local <4 x half> @test_vrev64_f16(<4 x half> %a) {
+entry:
+  %shuffle.i = shufflevector <4 x half> %a, <4 x half> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+  ret <4 x half> %shuffle.i
+}
+
+define dso_local <8 x half> @test_vrev64q_f16(<8 x half> %a) {
+entry:
+  %shuffle.i = shufflevector <8 x half> %a, <8 x half> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
+  ret <8 x half> %shuffle.i
+}
 
 declare <4 x half> @llvm.fabs.v4f16(<4 x half>)
 declare <8 x half> @llvm.fabs.v8f16(<8 x half>)