[llvm] r339533 - [SelectionDAG] In PromoteFloatRes_BITCAST, insert a bitcast before the fp16_to_fp in case the input type isn't an i16.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 12 22:26:50 PDT 2018
Author: ctopper
Date: Sun Aug 12 22:26:49 2018
New Revision: 339533
URL: http://llvm.org/viewvc/llvm-project?rev=339533&view=rev
Log:
[SelectionDAG] In PromoteFloatRes_BITCAST, insert a bitcast before the fp16_to_fp in case the input type isn't an i16.
The bitcast can be further legalized as needed.
Fixes PR38533.
Added:
llvm/trunk/test/CodeGen/X86/pr38533.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=339533&r1=339532&r2=339533&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Sun Aug 12 22:26:49 2018
@@ -1941,8 +1941,10 @@ void DAGTypeLegalizer::PromoteFloatResul
SDValue DAGTypeLegalizer::PromoteFloatRes_BITCAST(SDNode *N) {
EVT VT = N->getValueType(0);
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
- return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT,
- N->getOperand(0));
+ // Input type isn't guaranteed to be i16 so bitcast if not. The bitcast
+ // will be legalized further if necessary.
+ SDValue Cast = DAG.getBitcast(MVT::i16, N->getOperand(0));
+ return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT, Cast);
}
SDValue DAGTypeLegalizer::PromoteFloatRes_ConstantFP(SDNode *N) {
Added: llvm/trunk/test/CodeGen/X86/pr38533.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr38533.ll?rev=339533&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr38533.ll (added)
+++ llvm/trunk/test/CodeGen/X86/pr38533.ll Sun Aug 12 22:26:49 2018
@@ -0,0 +1,11 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s
+
+define void @constant_fold_vector_to_half() {
+; CHECK-LABEL: constant_fold_vector_to_half:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movw $16384, (%rax) # imm = 0x4000
+; CHECK-NEXT: retq
+ store volatile half bitcast (<4 x i4> <i4 0, i4 0, i4 0, i4 4> to half), half* undef
+ ret void
+}
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