[llvm] r339525 - DAG: Check no-signed-zeros instead of unsafe-fp-math
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 12 12:09:13 PDT 2018
Author: arsenm
Date: Sun Aug 12 12:09:12 2018
New Revision: 339525
URL: http://llvm.org/viewvc/llvm-project?rev=339525&view=rev
Log:
DAG: Check no-signed-zeros instead of unsafe-fp-math
Addresses fixme, although this should still be checking individual
operand flags.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/test/CodeGen/AMDGPU/fmax_legacy.ll
llvm/trunk/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll
llvm/trunk/test/CodeGen/AMDGPU/fmin_legacy.ll
llvm/trunk/test/CodeGen/NVPTX/bug22322.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=339525&r1=339524&r2=339525&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Aug 12 12:09:12 2018
@@ -7283,10 +7283,10 @@ SDValue DAGCombiner::visitSELECT(SDNode
// NaN.
//
- // FIXME: Instead of testing for UnsafeFPMath, this should be checking for
- // no signed zeros as well as no nans.
+ // FIXME: This should be checking for no signed zeros on individual
+ // operands, as well as no nans.
const TargetOptions &Options = DAG.getTarget().Options;
- if (Options.UnsafeFPMath && VT.isFloatingPoint() && N0.hasOneUse() &&
+ if (Options.NoSignedZerosFPMath && VT.isFloatingPoint() && N0.hasOneUse() &&
DAG.isKnownNeverNaN(N1) && DAG.isKnownNeverNaN(N2)) {
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
Modified: llvm/trunk/test/CodeGen/AMDGPU/fmax_legacy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/fmax_legacy.ll?rev=339525&r1=339524&r2=339525&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/fmax_legacy.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/fmax_legacy.ll Sun Aug 12 12:09:12 2018
@@ -1,9 +1,7 @@
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-SAFE -check-prefix=FUNC %s
-; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-; FIXME: Should replace unsafe-fp-math with no signed zeros.
-
declare i32 @llvm.r600.read.tidig.x() #1
; FUNC-LABEL: @test_fmax_legacy_uge_f32
Modified: llvm/trunk/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll?rev=339525&r1=339524&r2=339525&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/fmin_fmax_legacy.amdgcn.ll Sun Aug 12 12:09:12 2018
@@ -1,7 +1,5 @@
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-SAFE -check-prefix=GCN %s
-; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-NONAN -check-prefix=GCN %s
-
-; FIXME: Should replace unsafe-fp-math with no signed zeros.
+; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-NONAN -check-prefix=GCN %s
; GCN-LABEL: {{^}}min_fneg_select_regression_0:
; GCN-SAFE: v_max_legacy_f32_e64 [[MIN:v[0-9]+]], -1.0, -v0
Modified: llvm/trunk/test/CodeGen/AMDGPU/fmin_legacy.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/fmin_legacy.ll?rev=339525&r1=339524&r2=339525&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/fmin_legacy.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/fmin_legacy.ll Sun Aug 12 12:09:12 2018
@@ -1,9 +1,7 @@
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
-; FIXME: Should replace unsafe-fp-math with no signed zeros.
-
declare i32 @llvm.r600.read.tidig.x() #1
; The two inputs to the instruction are different SGPRs from the same
Modified: llvm/trunk/test/CodeGen/NVPTX/bug22322.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/bug22322.ll?rev=339525&r1=339524&r2=339525&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/bug22322.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/bug22322.ll Sun Aug 12 12:09:12 2018
@@ -51,7 +51,7 @@ declare void @llvm.lifetime.start.p0i8(i
; Function Attrs: nounwind
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #2
-attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="true" "use-soft-float"="false" }
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "stack-protector-buffer-size"="8" "no-signed-zeros-fp-math"="true" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }
attributes #2 = { nounwind }
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