[llvm] r339496 - [X86] Change the MOV32ri64 pseudo instruction to def a GR64 directly instead of wrapping it in a SUBREG_TO_REG.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 10 22:33:01 PDT 2018
Author: ctopper
Date: Fri Aug 10 22:33:00 2018
New Revision: 339496
URL: http://llvm.org/viewvc/llvm-project?rev=339496&view=rev
Log:
[X86] Change the MOV32ri64 pseudo instruction to def a GR64 directly instead of wrapping it in a SUBREG_TO_REG.
Now we switch to the subregister in expandPostRAPseudos where we already switched the opcode.
This simplifies a few isel patterns that used the pseudo directly. And magically seems to have improved our ability to CSE it in the undef-label.ll test.
Modified:
llvm/trunk/lib/Target/X86/X86InstrCompiler.td
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/test/CodeGen/X86/abi-isel.ll
llvm/trunk/test/CodeGen/X86/atomic_mi.ll
llvm/trunk/test/CodeGen/X86/conditional-tailcall-samedest.mir
llvm/trunk/test/CodeGen/X86/flags-copy-lowering.mir
llvm/trunk/test/CodeGen/X86/licm-nested.ll
llvm/trunk/test/CodeGen/X86/select-mmx.ll
llvm/trunk/test/CodeGen/X86/select_const.ll
llvm/trunk/test/CodeGen/X86/tail-call-conditional.mir
llvm/trunk/test/CodeGen/X86/undef-label.ll
llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir
Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=339496&r1=339495&r2=339496&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Fri Aug 10 22:33:00 2018
@@ -319,16 +319,14 @@ def MOV64ImmSExti8 : I<0, Pseudo, (outs
// that would make it more difficult to rematerialize.
let isReMaterializable = 1, isAsCheapAsAMove = 1,
isPseudo = 1, hasSideEffects = 0, SchedRW = [WriteMove] in
-def MOV32ri64 : I<0, Pseudo, (outs GR32:$dst), (ins i64i32imm:$src), "", []>;
+def MOV32ri64 : I<0, Pseudo, (outs GR64:$dst), (ins i64i32imm:$src), "", []>;
// This 64-bit pseudo-move can be used for both a 64-bit constant that is
// actually the zero-extension of a 32-bit constant and for labels in the
// x86-64 small code model.
def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [imm, X86Wrapper]>;
-let AddedComplexity = 1 in
-def : Pat<(i64 mov64imm32:$src),
- (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
+def : Pat<(i64 mov64imm32:$src), (MOV32ri64 mov64imm32:$src)>;
// Use sbb to materialize carry bit.
let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
@@ -2060,13 +2058,7 @@ let Predicates = [HasBMI, NoTBM] in {
def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
(BEXTR32rm addr:$src1, (MOV32ri imm:$src2))>;
def : Pat<(X86bextr GR64:$src1, mov64imm32:$src2),
- (BEXTR64rr GR64:$src1,
- (SUBREG_TO_REG (i64 0),
- (MOV32ri64 mov64imm32:$src2),
- sub_32bit))>;
+ (BEXTR64rr GR64:$src1, (MOV32ri64 mov64imm32:$src2))>;
def : Pat<(X86bextr (loadi64 addr:$src1), mov64imm32:$src2),
- (BEXTR64rm addr:$src1,
- (SUBREG_TO_REG (i64 0),
- (MOV32ri64 mov64imm32:$src2),
- sub_32bit))>;
+ (BEXTR64rm addr:$src1, (MOV32ri64 mov64imm32:$src2))>;
} // HasBMI, NoTBM
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=339496&r1=339495&r2=339496&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Aug 10 22:33:00 2018
@@ -4267,9 +4267,14 @@ bool X86InstrInfo::expandPostRAPseudo(Ma
case X86::VMOVUPSZ256mr_NOVLX:
return expandNOVLXStore(MIB, &getRegisterInfo(), get(X86::VMOVUPSYmr),
get(X86::VEXTRACTF64x4Zmr), X86::sub_ymm);
- case X86::MOV32ri64:
+ case X86::MOV32ri64: {
+ unsigned Reg = MIB->getOperand(0).getReg();
+ unsigned Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
MI.setDesc(get(X86::MOV32ri));
+ MIB->getOperand(0).setReg(Reg32);
+ MIB.addReg(Reg, RegState::ImplicitDefine);
return true;
+ }
// KNL does not recognize dependency-breaking idioms for mask registers,
// so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
Modified: llvm/trunk/test/CodeGen/X86/abi-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/abi-isel.ll?rev=339496&r1=339495&r2=339496&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/abi-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/abi-isel.ll Fri Aug 10 22:33:00 2018
@@ -7751,8 +7751,8 @@ define i8* @bam02() nounwind {
;
; LINUX-64-PIC-LABEL: bam02:
; LINUX-64-PIC: # %bb.0: # %entry
+; LINUX-64-PIC-NEXT: movq ptr@{{.*}}(%rip), %rcx
; LINUX-64-PIC-NEXT: movl $262144, %eax # imm = 0x40000
-; LINUX-64-PIC-NEXT: movq ptr at GOTPCREL(%rip), %rcx
; LINUX-64-PIC-NEXT: addq (%rcx), %rax
; LINUX-64-PIC-NEXT: retq
;
@@ -7781,22 +7781,22 @@ define i8* @bam02() nounwind {
;
; DARWIN-64-STATIC-LABEL: bam02:
; DARWIN-64-STATIC: ## %bb.0: ## %entry
+; DARWIN-64-STATIC-NEXT: movq _ptr@{{.*}}(%rip), %rcx
; DARWIN-64-STATIC-NEXT: movl $262144, %eax ## imm = 0x40000
-; DARWIN-64-STATIC-NEXT: movq _ptr at GOTPCREL(%rip), %rcx
; DARWIN-64-STATIC-NEXT: addq (%rcx), %rax
; DARWIN-64-STATIC-NEXT: retq
;
; DARWIN-64-DYNAMIC-LABEL: bam02:
; DARWIN-64-DYNAMIC: ## %bb.0: ## %entry
+; DARWIN-64-DYNAMIC-NEXT: movq _ptr@{{.*}}(%rip), %rcx
; DARWIN-64-DYNAMIC-NEXT: movl $262144, %eax ## imm = 0x40000
-; DARWIN-64-DYNAMIC-NEXT: movq _ptr at GOTPCREL(%rip), %rcx
; DARWIN-64-DYNAMIC-NEXT: addq (%rcx), %rax
; DARWIN-64-DYNAMIC-NEXT: retq
;
; DARWIN-64-PIC-LABEL: bam02:
; DARWIN-64-PIC: ## %bb.0: ## %entry
+; DARWIN-64-PIC-NEXT: movq _ptr@{{.*}}(%rip), %rcx
; DARWIN-64-PIC-NEXT: movl $262144, %eax ## imm = 0x40000
-; DARWIN-64-PIC-NEXT: movq _ptr at GOTPCREL(%rip), %rcx
; DARWIN-64-PIC-NEXT: addq (%rcx), %rax
; DARWIN-64-PIC-NEXT: retq
@@ -7946,8 +7946,8 @@ define i8* @bam05() nounwind {
;
; LINUX-64-PIC-LABEL: bam05:
; LINUX-64-PIC: # %bb.0: # %entry
+; LINUX-64-PIC-NEXT: movq dptr@{{.*}}(%rip), %rcx
; LINUX-64-PIC-NEXT: movl $262144, %eax # imm = 0x40000
-; LINUX-64-PIC-NEXT: movq dptr at GOTPCREL(%rip), %rcx
; LINUX-64-PIC-NEXT: addq (%rcx), %rax
; LINUX-64-PIC-NEXT: retq
;
Modified: llvm/trunk/test/CodeGen/X86/atomic_mi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atomic_mi.ll?rev=339496&r1=339495&r2=339496&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/atomic_mi.ll (original)
+++ llvm/trunk/test/CodeGen/X86/atomic_mi.ll Fri Aug 10 22:33:00 2018
@@ -2050,8 +2050,8 @@ define void @fadd_64g() {
define void @fadd_32imm() {
; X64-LABEL: fadd_32imm:
; X64: # %bb.0:
-; X64-NEXT: movl $3735928559, %eax # imm = 0xDEADBEEF
; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; X64-NEXT: movl $3735928559, %eax # imm = 0xDEADBEEF
; X64-NEXT: addss (%rax), %xmm0
; X64-NEXT: movss %xmm0, (%rax)
; X64-NEXT: retq
@@ -2082,8 +2082,8 @@ define void @fadd_32imm() {
define void @fadd_64imm() {
; X64-LABEL: fadd_64imm:
; X64: # %bb.0:
-; X64-NEXT: movl $3735928559, %eax # imm = 0xDEADBEEF
; X64-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
+; X64-NEXT: movl $3735928559, %eax # imm = 0xDEADBEEF
; X64-NEXT: addsd (%rax), %xmm0
; X64-NEXT: movsd %xmm0, (%rax)
; X64-NEXT: retq
Modified: llvm/trunk/test/CodeGen/X86/conditional-tailcall-samedest.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/conditional-tailcall-samedest.mir?rev=339496&r1=339495&r2=339496&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/conditional-tailcall-samedest.mir (original)
+++ llvm/trunk/test/CodeGen/X86/conditional-tailcall-samedest.mir Fri Aug 10 22:33:00 2018
@@ -124,7 +124,7 @@ body: |
JMP_1 %bb.3
bb.3.init.check.i:
- dead $edi = MOV32ri64 @static_local_guard, implicit-def $rdi
+ dead $edi = MOV32ri @static_local_guard, implicit-def $rdi
TCRETURNdi64 @initialize_static_local, 0, csr_64, implicit $rsp, implicit $rdi
bb.4.sw.bb2:
Modified: llvm/trunk/test/CodeGen/X86/flags-copy-lowering.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/flags-copy-lowering.mir?rev=339496&r1=339495&r2=339496&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/flags-copy-lowering.mir (original)
+++ llvm/trunk/test/CodeGen/X86/flags-copy-lowering.mir Fri Aug 10 22:33:00 2018
@@ -144,12 +144,12 @@ body: |
; CHECK-NEXT: JMP_1 %bb.3
bb.1:
- %3:gr32 = MOV32ri64 42
+ %3:gr32 = MOV32ri 42
$eax = COPY %3
RET 0, $eax
bb.2:
- %4:gr32 = MOV32ri64 43
+ %4:gr32 = MOV32ri 43
$eax = COPY %4
RET 0, $eax
@@ -205,12 +205,12 @@ body: |
RET 0, $eax
bb.2:
- %3:gr32 = MOV32ri64 42
+ %3:gr32 = MOV32ri 42
$eax = COPY %3
RET 0, $eax
bb.3:
- %4:gr32 = MOV32ri64 43
+ %4:gr32 = MOV32ri 43
$eax = COPY %4
RET 0, $eax
@@ -991,12 +991,12 @@ body: |
; CHECK-NEXT: JMP_1 %bb.3
bb.1:
- %5:gr32 = MOV32ri64 42
+ %5:gr32 = MOV32ri 42
$eax = COPY %5
RET 0, $eax
bb.2:
- %6:gr32 = MOV32ri64 43
+ %6:gr32 = MOV32ri 43
$eax = COPY %6
RET 0, $eax
@@ -1045,12 +1045,12 @@ body: |
; CHECK-NEXT: JMP_1 %bb.2
bb.1:
- %3:gr32 = MOV32ri64 42
+ %3:gr32 = MOV32ri 42
$eax = COPY %3
RET 0, $eax
bb.2:
- %4:gr32 = MOV32ri64 43
+ %4:gr32 = MOV32ri 43
$eax = COPY %4
RET 0, $eax
Modified: llvm/trunk/test/CodeGen/X86/licm-nested.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/licm-nested.ll?rev=339496&r1=339495&r2=339496&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/licm-nested.ll (original)
+++ llvm/trunk/test/CodeGen/X86/licm-nested.ll Fri Aug 10 22:33:00 2018
@@ -1,5 +1,5 @@
; REQUIRES: asserts
-; RUN: llc -mtriple=x86_64-apple-darwin < %s -o /dev/null -stats -info-output-file - | grep "hoisted out of loops" | grep 5
+; RUN: llc -mtriple=x86_64-apple-darwin < %s -o /dev/null -stats -info-output-file - | grep "hoisted out of loops" | grep 3
; MachineLICM should be able to hoist the symbolic addresses out of
; the inner loops.
Modified: llvm/trunk/test/CodeGen/X86/select-mmx.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/select-mmx.ll?rev=339496&r1=339495&r2=339496&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/select-mmx.ll (original)
+++ llvm/trunk/test/CodeGen/X86/select-mmx.ll Fri Aug 10 22:33:00 2018
@@ -17,8 +17,8 @@ define i64 @test47(i64 %arg) {
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: testq %rdi, %rdi
; X64-NEXT: movl $7, %ecx
-; X64-NEXT: cmoveq %rcx, %rax
-; X64-NEXT: movq %rax, %mm0
+; X64-NEXT: cmovneq %rax, %rcx
+; X64-NEXT: movq %rcx, %mm0
; X64-NEXT: psllw %mm0, %mm0
; X64-NEXT: movq %mm0, %rax
; X64-NEXT: retq
Modified: llvm/trunk/test/CodeGen/X86/select_const.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/select_const.ll?rev=339496&r1=339495&r2=339496&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/select_const.ll (original)
+++ llvm/trunk/test/CodeGen/X86/select_const.ll Fri Aug 10 22:33:00 2018
@@ -484,9 +484,9 @@ define i64 @opaque_constant(i1 %cond, i6
; CHECK-LABEL: opaque_constant:
; CHECK: # %bb.0:
; CHECK-NEXT: testb $1, %dil
-; CHECK-NEXT: movl $23, %ecx
-; CHECK-NEXT: movq $-4, %rax
-; CHECK-NEXT: cmoveq %rcx, %rax
+; CHECK-NEXT: movq $-4, %rcx
+; CHECK-NEXT: movl $23, %eax
+; CHECK-NEXT: cmovneq %rcx, %rax
; CHECK-NEXT: movabsq $4294967297, %rcx # imm = 0x100000001
; CHECK-NEXT: andq %rcx, %rax
; CHECK-NEXT: xorl %edx, %edx
Modified: llvm/trunk/test/CodeGen/X86/tail-call-conditional.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-call-conditional.mir?rev=339496&r1=339495&r2=339496&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tail-call-conditional.mir (original)
+++ llvm/trunk/test/CodeGen/X86/tail-call-conditional.mir Fri Aug 10 22:33:00 2018
@@ -79,7 +79,7 @@ body: |
TCRETURNdi64 @f2, 0, csr_64, implicit $rsp, implicit $rdi, implicit $rsi
bb.4:
- dead $eax = MOV32ri64 123, implicit-def $rax
+ dead $eax = MOV32ri 123, implicit-def $rax
RET 0, $rax
...
Modified: llvm/trunk/test/CodeGen/X86/undef-label.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/undef-label.ll?rev=339496&r1=339495&r2=339496&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/undef-label.ll (original)
+++ llvm/trunk/test/CodeGen/X86/undef-label.ll Fri Aug 10 22:33:00 2018
@@ -10,20 +10,17 @@ define void @xyz() {
; CHECK-LABEL: xyz:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl $g, %eax
-; CHECK-NEXT: movq %rax, %xmm1
-; CHECK-NEXT: xorps %xmm0, %xmm0
-; CHECK-NEXT: ucomisd %xmm0, %xmm1
+; CHECK-NEXT: movq %rax, %xmm0
+; CHECK-NEXT: xorps %xmm1, %xmm1
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
; CHECK-NEXT: jne .LBB0_1
-; CHECK-NEXT: jnp .LBB0_3
-; CHECK-NEXT: .LBB0_1: # %foo.preheader
-; CHECK-NEXT: movl $g, %eax
-; CHECK-NEXT: movq %rax, %xmm1
+; CHECK-NEXT: jnp .LBB0_2
; CHECK-NEXT: .p2align 4, 0x90
-; CHECK-NEXT: .LBB0_2: # %foo
+; CHECK-NEXT: .LBB0_1: # %foo
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ucomisd %xmm0, %xmm1
-; CHECK-NEXT: ja .LBB0_2
-; CHECK-NEXT: .LBB0_3: # %bar
+; CHECK-NEXT: ucomisd %xmm1, %xmm0
+; CHECK-NEXT: ja .LBB0_1
+; CHECK-NEXT: .LBB0_2: # %bar
; CHECK-NEXT: retq
entry:
br i1 fcmp oeq (double bitcast (i64 ptrtoint (i32* @g to i64) to double), double 0.000000e+00), label %bar, label %foo
Modified: llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir?rev=339496&r1=339495&r2=339496&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir (original)
+++ llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir Fri Aug 10 22:33:00 2018
@@ -246,7 +246,7 @@ body: |
liveins: $ecx
MOV32mr $rip, 1, _, @m, _, $ecx, debug-location !43 :: (store 4 into @m, !tbaa !44)
- dead undef $edi = MOV32ri64 @.str, implicit-def $rdi, debug-location !46
+ dead undef $edi = MOV32ri @.str, implicit-def $rdi, debug-location !46
dead $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags, implicit-def $al, debug-location !47
$esi = MOV32rr killed $ecx, debug-location !46
CALL64pcrel32 @printf, csr_64, implicit $rsp, implicit $rdi, implicit $esi, implicit $al, implicit-def $rsp, implicit-def dead $eax, debug-location !46
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