[PATCH] D50592: Add check for tied operands

[Sid Manning via Phabricator via llvm-commits]

sidneym created this revision.
sidneym added reviewers: ruiu, kparzysz, bcain, shankare.

The "tied" attribute was not being checked.
When the registers mismatched no error is generated unless asserts are enabled.


Repository:
  rL LLVM

https://reviews.llvm.org/D50592

Files:
  lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
  test/MC/Hexagon/tied-ops.s


Index: test/MC/Hexagon/tied-ops.s
===================================================================
--- /dev/null
+++ test/MC/Hexagon/tied-ops.s
@@ -0,0 +1,7 @@
+# RUN: llvm-mc -arch=hexagon -filetype=asm %s 2> %t; FileCheck %s < %t
+
+# Check that tied operands are caught
+
+	{ r0 = sub(##_start, asl(r1, #1)) }
+# CHECK: error: invalid operand for instruction
+
Index: lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
===================================================================
--- lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
+++ lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
@@ -581,6 +581,7 @@
   case Match_MnemonicFail:
     return Error(IDLoc, "unrecognized instruction");
   case Match_InvalidOperand:
+  case Match_InvalidTiedOperand:
     SMLoc ErrorLoc = IDLoc;
     if (ErrorInfo != ~0U) {
       if (ErrorInfo >= InstOperands.size())


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