[PATCH] D50578: [DAGCombiner][Mips] Don't combine bitcast+store after LegalOperations when the store is volatile, if the resulting store isn't Legal

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: efriedma, sdardis.
Herald added subscribers: atanasyan, arichardson.

Previously we allowed the store to be Custom. But without knowing for sure that the Custom handling won't split the store, we shouldn't convert a volatile store. We also probably shouldn't be creating a store the requires custom handling after LegalizeOps. This could lead to an infinite loop if the custom handling was to insert a bitcast. Though I guess isStoreBitCastBeneficial could be used to block such a loop.

The test changes here are due to the volatile part of this. The stores in the test are all volatile and i32 stores are marked custom, So we are no longer converting them

This is related to https://reviews.llvm.org/D50491 where I was trying to allow some bitcasting of volatile loads.


https://reviews.llvm.org/D50578

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
  test/CodeGen/Mips/cconv/arguments-hard-float.ll


Index: test/CodeGen/Mips/cconv/arguments-hard-float.ll
===================================================================
--- test/CodeGen/Mips/cconv/arguments-hard-float.ll
+++ test/CodeGen/Mips/cconv/arguments-hard-float.ll
@@ -125,9 +125,11 @@
 ; I've yet to find a reference in the documentation about this but GCC uses up
 ; the remaining two argument slots in the GPR's first. We'll do the same for
 ; compatibility.
-; O32-DAG:           sw $6, 12([[R1]])
+; O32-DAG:           mtc1 $6, $f0
+; O32-DAG:           swc1 $f0, 12([[R1]])
 ; NEW-DAG:           swc1 $f14, 12([[R1]])
-; O32-DAG:           sw $7, 16([[R1]])
+; O32-DAG:           mtc1 $7, $f0
+; O32-DAG:           swc1 $f0, 16([[R1]])
 ; NEW-DAG:           swc1 $f15, 16([[R1]])
 
 ; O32 is definitely out of registers now and switches to the stack.
@@ -207,5 +209,6 @@
 ; MD00305 and GCC disagree on this one. MD00305 says that floats are treated
 ; as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
 ; aligned and occupying one slot. We'll use GCC's definition.
-; O32-DAG:           sw $5, 4([[R2]])
+; O32-DAG:           mtc1 $5, $f0
+; O32-DAG:           swc1 $f0, 4([[R2]])
 ; NEW-DAG:           swc1 $f13, 4([[R2]])
Index: test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
===================================================================
--- test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
+++ test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll
@@ -111,7 +111,8 @@
 
 ; The first four arguments are the same in O32/N32/N64.
 ; The non-variable portion should be unaffected.
-; O32-DAG:           sw $4, 4([[R2]])
+; O32-DAG:           mtc1 $4, $f0
+; O32-DAG:           swc1 $f0, 4([[R2]])
 ; NEW-DAG:           swc1 $f12, 4([[R2]])
 
 ; The varargs portion is dumped to stack
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -14641,7 +14641,7 @@
       ST->isUnindexed()) {
     EVT SVT = Value.getOperand(0).getValueType();
     if (((!LegalOperations && !ST->isVolatile()) ||
-         TLI.isOperationLegalOrCustom(ISD::STORE, SVT)) &&
+         TLI.isOperationLegal(ISD::STORE, SVT)) &&
         TLI.isStoreBitCastBeneficial(Value.getValueType(), SVT)) {
       unsigned OrigAlign = ST->getAlignment();
       bool Fast = false;


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