[PATCH] D50572: DAG: Handle odd vector sizes in calling conv splitting

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Aug 10 10:44:17 PDT 2018


arsenm created this revision.
arsenm added reviewers: bogner, sdardis.
Herald added subscribers: tpr, nhaehnle, wdng.

This already worked if only one register piece was used,
but didn't if a type was split into multiple, unequal
sized pieces.

      

Fixes not splitting 3i16/v3f16 into two registers for
AMDGPU.

      

This will also allow fixing the ABI for 16-bit vectors
in a future commit so that it's the same for all subtargets.


https://reviews.llvm.org/D50572

Files:
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/Target/AMDGPU/SIISelLowering.cpp
  test/CodeGen/AMDGPU/call-argument-types.ll
  test/CodeGen/AMDGPU/fcanonicalize.f16.ll
  test/CodeGen/AMDGPU/function-args.ll
  test/CodeGen/AMDGPU/function-returns.ll
  test/CodeGen/AMDGPU/mad-mix-lo.ll

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