[llvm] r339381 - [RISC-V] Fixed alias for addi x2, x2, 0

[Ana Pazos via llvm-commits]

Author: apazos
Date: Thu Aug  9 13:51:53 2018
New Revision: 339381

URL: http://llvm.org/viewvc/llvm-project?rev=339381&view=rev
Log:
[RISC-V] Fixed alias for addi x2, x2, 0

A missing check for non-zero immediate in MCOperandPredicate
caused c.addi16sp sp, 0 to be selected which is not a valid
instruction.

Modified:
    llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td
    llvm/trunk/test/MC/RISCV/rv32c-aliases-valid.s

Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td?rev=339381&r1=339380&r2=339381&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td Thu Aug  9 13:51:53 2018
@@ -187,7 +187,7 @@ def simm10_lsb0000nonzero : Operand<XLen
     int64_t Imm;
     if (!MCOp.evaluateAsConstantImm(Imm))
       return false;
-    return isShiftedInt<6, 4>(Imm);
+    return isShiftedInt<6, 4>(Imm) && (Imm != 0);
   }];
 }
 

Modified: llvm/trunk/test/MC/RISCV/rv32c-aliases-valid.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/rv32c-aliases-valid.s?rev=339381&r1=339380&r2=339381&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/rv32c-aliases-valid.s (original)
+++ llvm/trunk/test/MC/RISCV/rv32c-aliases-valid.s Thu Aug  9 13:51:53 2018
@@ -60,3 +60,6 @@ li x12, -0x80000000
 li x12, 0x80000000
 # CHECK-EXPAND: c.li a2, -1
 li x12, 0xFFFFFFFF
+
+# CHECK-EXPAND: c.mv sp, sp
+addi x2, x2, 0