[PATCH] D46179: [X86] Lowering addus/subus intrinsics to native IR (LLVM part)

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:32900
+       (Subtarget.useBWIRegs() && (VT == MVT::v64i8 || VT == MVT::v32i16 ||
+                                   VT == MVT::v16i32 || MVT::v8i64)))) {
+    ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
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Why are v16i32 and v8i64 included here? We don't have saturating add/sub for those types do we?


Repository:
  rL LLVM

https://reviews.llvm.org/D46179