[PATCH] D50514: [7.0 branch] Update release notes (SystemZ, TableGen)

[Ulrich Weigand via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL339355: [7.0 branch] Update release notes (SystemZ, TableGen) (authored by uweigand, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D50514?vs=159930&id=159938#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D50514

Files:
  llvm/branches/release_70/docs/ReleaseNotes.rst


Index: llvm/branches/release_70/docs/ReleaseNotes.rst
===================================================================
--- llvm/branches/release_70/docs/ReleaseNotes.rst
+++ llvm/branches/release_70/docs/ReleaseNotes.rst
@@ -161,6 +161,26 @@
 
  During this release ...
 
+Changes to the SystemZ Target
+-----------------------------
+
+During this release the SystemZ target has:
+
+* Added support for vector registers in inline asm statements.
+
+* Added support for stackmaps, patchpoints, and the anyregcc
+  calling convention.
+
+* Changed the default function alignment to 16 bytes.
+
+* Improved codegen for condition code handling.
+
+* Improved instruction scheduling and microarchitecture tuning for z13/z14.
+
+* Fixed support for generating GCOV coverage data.
+
+* Fixed some codegen bugs.
+
 Changes to the X86 Target
 -------------------------
 
@@ -198,6 +218,10 @@
 
 * The SETCCE opcode has now been removed in favor of SETCCCARRY.
 
+* TableGen now supports multi-alternative pattern fragments via the PatFrags
+  class.  PatFrag is now derived from PatFrags, which may require minor
+  changes to backends that directly access PatFrag members.
+
 External Open Source Projects Using LLVM 7
 ==========================================
 


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