[PATCH] D50496: [RISCV] Implment pseudo instructions for load/store from a symbol address.
Kito Cheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 9 01:59:39 PDT 2018
kito-cheng updated this revision to Diff 159879.
kito-cheng added a comment.
- Add default case in switch.
https://reviews.llvm.org/D50496
Files:
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
lib/Target/RISCV/RISCVInstrFormats.td
lib/Target/RISCV/RISCVInstrInfo.td
lib/Target/RISCV/RISCVInstrInfoD.td
lib/Target/RISCV/RISCVInstrInfoF.td
test/MC/RISCV/rv64i-pseudos.s
test/MC/RISCV/rvd-pseudos.s
test/MC/RISCV/rvf-pseudos.s
test/MC/RISCV/rvi-pseudos.s
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D50496.159879.patch
Type: text/x-patch
Size: 15623 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180809/33c663d5/attachment.bin>
More information about the llvm-commits
mailing list