[PATCH] D50326: [ARM] FP16: vector VMUL variants

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added inline comments.


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Comment at: test/CodeGen/ARM/armv8.2a-fp16-vector-intrinsics.ll:996
+  ret <8 x half> %mul
+}
 
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SjoerdMeijer wrote:
> samparker wrote:
> > Should there not also be a test where both inputs are v8f16?
> ah, I now see what you mean. This is the test and IR for ACLE intrinsic:
> 
>   float16x8_t vmulq_lane_f16 (float16x8_t a, float16x4_t v, const int lane)
> 
> but yes, the pattern would also match for a pattern where the 2nd operand is a v8f16.
> 
The shufflevector is creating a  8 x half vector here, with half the elements undef because we pass in a 4 x half, so it actually looks all okay here?


https://reviews.llvm.org/D50326