[llvm] r339146 - [TargetLowering] Use pre-computed Shift value type in BuildUDIV (NFCI)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 7 07:40:21 PDT 2018
Author: rksimon
Date: Tue Aug 7 07:40:21 2018
New Revision: 339146
URL: http://llvm.org/viewvc/llvm-project?rev=339146&view=rev
Log:
[TargetLowering] Use pre-computed Shift value type in BuildUDIV (NFCI)
This was missed in D49248
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=339146&r1=339145&r2=339146&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Aug 7 07:40:21 2018
@@ -3551,10 +3551,8 @@ SDValue TargetLowering::BuildUDIV(SDNode
bool IsAfterLegalization,
SmallVectorImpl<SDNode *> &Created) const {
SDLoc dl(N);
- auto &DL = DAG.getDataLayout();
-
EVT VT = N->getValueType(0);
- EVT ShVT = getShiftAmountTy(VT, DL);
+ EVT ShVT = getShiftAmountTy(VT, DAG.getDataLayout());
// Check to see if we can do this.
// FIXME: We should be more aggressive here.
@@ -3669,13 +3667,11 @@ SDValue TargetLowering::BuildUDIV(SDNode
// For vectors we might have a mix of non-NPQ/NPQ paths, so use
// MULHU to act as a SRL-by-1 for NPQ, else multiply by zero.
- if (VT.isVector()) {
+ if (VT.isVector())
NPQ = GetMULHU(NPQ, NPQFactor);
- } else {
- NPQ = DAG.getNode(
- ISD::SRL, dl, VT, NPQ,
- DAG.getConstant(1, dl, getShiftAmountTy(NPQ.getValueType(), DL)));
- }
+ else
+ NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ, DAG.getConstant(1, dl, ShVT));
+
Created.push_back(NPQ.getNode());
Q = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
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