[llvm] r339022 - AMDGPU: Rename check prefixes in test

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Mon Aug  6 08:16:12 2018
New Revision: 339022

URL: http://llvm.org/viewvc/llvm-project?rev=339022&view=rev
Log:
AMDGPU: Rename check prefixes in test

Will avoid noisy diff in future change.

Modified:
    llvm/trunk/test/CodeGen/AMDGPU/fp-classify.ll

Modified: llvm/trunk/test/CodeGen/AMDGPU/fp-classify.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/fp-classify.ll?rev=339022&r1=339021&r2=339022&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/fp-classify.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/fp-classify.ll Mon Aug  6 08:16:12 2018
@@ -1,14 +1,14 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
 
 declare float @llvm.fabs.f32(float) #1
 declare double @llvm.fabs.f64(double) #1
 
-; SI-LABEL: {{^}}test_isinf_pattern:
-; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x204{{$}}
-; SI: v_cmp_class_f32_e32 vcc, s{{[0-9]+}}, [[MASK]]
-; SI-NOT: v_cmp
-; SI: s_endpgm
+; GCN-LABEL: {{^}}test_isinf_pattern:
+; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x204{{$}}
+; GCN: v_cmp_class_f32_e32 vcc, s{{[0-9]+}}, [[MASK]]
+; GCN-NOT: v_cmp
+; GCN: s_endpgm
 define amdgpu_kernel void @test_isinf_pattern(i32 addrspace(1)* nocapture %out, float %x) #0 {
   %fabs = tail call float @llvm.fabs.f32(float %x) #1
   %cmp = fcmp oeq float %fabs, 0x7FF0000000000000
@@ -17,9 +17,9 @@ define amdgpu_kernel void @test_isinf_pa
   ret void
 }
 
-; SI-LABEL: {{^}}test_not_isinf_pattern_0:
-; SI-NOT: v_cmp_class
-; SI: s_endpgm
+; GCN-LABEL: {{^}}test_not_isinf_pattern_0:
+; GCN-NOT: v_cmp_class
+; GCN: s_endpgm
 define amdgpu_kernel void @test_not_isinf_pattern_0(i32 addrspace(1)* nocapture %out, float %x) #0 {
   %fabs = tail call float @llvm.fabs.f32(float %x) #1
   %cmp = fcmp ueq float %fabs, 0x7FF0000000000000
@@ -28,9 +28,9 @@ define amdgpu_kernel void @test_not_isin
   ret void
 }
 
-; SI-LABEL: {{^}}test_not_isinf_pattern_1:
-; SI-NOT: v_cmp_class
-; SI: s_endpgm
+; GCN-LABEL: {{^}}test_not_isinf_pattern_1:
+; GCN-NOT: v_cmp_class
+; GCN: s_endpgm
 define amdgpu_kernel void @test_not_isinf_pattern_1(i32 addrspace(1)* nocapture %out, float %x) #0 {
   %fabs = tail call float @llvm.fabs.f32(float %x) #1
   %cmp = fcmp oeq float %fabs, 0xFFF0000000000000
@@ -39,12 +39,12 @@ define amdgpu_kernel void @test_not_isin
   ret void
 }
 
-; SI-LABEL: {{^}}test_isfinite_pattern_0:
-; SI-NOT: v_cmp
-; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1f8{{$}}
-; SI: v_cmp_class_f32_e32 vcc, s{{[0-9]+}}, [[MASK]]
-; SI-NOT: v_cmp
-; SI: s_endpgm
+; GCN-LABEL: {{^}}test_isfinite_pattern_0:
+; GCN-NOT: v_cmp
+; GCN: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1f8{{$}}
+; GCN: v_cmp_class_f32_e32 vcc, s{{[0-9]+}}, [[MASK]]
+; GCN-NOT: v_cmp
+; GCN: s_endpgm
 define amdgpu_kernel void @test_isfinite_pattern_0(i32 addrspace(1)* nocapture %out, float %x) #0 {
   %ord = fcmp ord float %x, 0.000000e+00
   %x.fabs = tail call float @llvm.fabs.f32(float %x) #1
@@ -56,9 +56,9 @@ define amdgpu_kernel void @test_isfinite
 }
 
 ; Use negative infinity
-; SI-LABEL: {{^}}test_isfinite_not_pattern_0:
-; SI-NOT: v_cmp_class_f32
-; SI: s_endpgm
+; GCN-LABEL: {{^}}test_isfinite_not_pattern_0:
+; GCN-NOT: v_cmp_class_f32
+; GCN: s_endpgm
 define amdgpu_kernel void @test_isfinite_not_pattern_0(i32 addrspace(1)* nocapture %out, float %x) #0 {
   %ord = fcmp ord float %x, 0.000000e+00
   %x.fabs = tail call float @llvm.fabs.f32(float %x) #1
@@ -70,9 +70,9 @@ define amdgpu_kernel void @test_isfinite
 }
 
 ; No fabs
-; SI-LABEL: {{^}}test_isfinite_not_pattern_1:
-; SI-NOT: v_cmp_class_f32
-; SI: s_endpgm
+; GCN-LABEL: {{^}}test_isfinite_not_pattern_1:
+; GCN-NOT: v_cmp_class_f32
+; GCN: s_endpgm
 define amdgpu_kernel void @test_isfinite_not_pattern_1(i32 addrspace(1)* nocapture %out, float %x) #0 {
   %ord = fcmp ord float %x, 0.000000e+00
   %ninf = fcmp une float %x, 0x7FF0000000000000
@@ -83,9 +83,9 @@ define amdgpu_kernel void @test_isfinite
 }
 
 ; fabs of different value
-; SI-LABEL: {{^}}test_isfinite_not_pattern_2:
-; SI-NOT: v_cmp_class_f32
-; SI: s_endpgm
+; GCN-LABEL: {{^}}test_isfinite_not_pattern_2:
+; GCN-NOT: v_cmp_class_f32
+; GCN: s_endpgm
 define amdgpu_kernel void @test_isfinite_not_pattern_2(i32 addrspace(1)* nocapture %out, float %x, float %y) #0 {
   %ord = fcmp ord float %x, 0.000000e+00
   %x.fabs = tail call float @llvm.fabs.f32(float %y) #1
@@ -97,9 +97,9 @@ define amdgpu_kernel void @test_isfinite
 }
 
 ; Wrong ordered compare type
-; SI-LABEL: {{^}}test_isfinite_not_pattern_3:
-; SI-NOT: v_cmp_class_f32
-; SI: s_endpgm
+; GCN-LABEL: {{^}}test_isfinite_not_pattern_3:
+; GCN-NOT: v_cmp_class_f32
+; GCN: s_endpgm
 define amdgpu_kernel void @test_isfinite_not_pattern_3(i32 addrspace(1)* nocapture %out, float %x) #0 {
   %ord = fcmp uno float %x, 0.000000e+00
   %x.fabs = tail call float @llvm.fabs.f32(float %x) #1
@@ -111,9 +111,9 @@ define amdgpu_kernel void @test_isfinite
 }
 
 ; Wrong unordered compare
-; SI-LABEL: {{^}}test_isfinite_not_pattern_4:
-; SI-NOT: v_cmp_class_f32
-; SI: s_endpgm
+; GCN-LABEL: {{^}}test_isfinite_not_pattern_4:
+; GCN-NOT: v_cmp_class_f32
+; GCN: s_endpgm
 define amdgpu_kernel void @test_isfinite_not_pattern_4(i32 addrspace(1)* nocapture %out, float %x) #0 {
   %ord = fcmp ord float %x, 0.000000e+00
   %x.fabs = tail call float @llvm.fabs.f32(float %x) #1