[PATCH] D50306: [AMDGPU] New buffer intrinsics

[Tim Renouf via Phabricator via llvm-commits]

tpr created this revision.
Herald added subscribers: llvm-commits, jfb, t-tye, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl, arsenm.

This commit adds new intrinsics

  llvm.amdgcn.raw.buffer.load
  llvm.amdgcn.raw.buffer.load.format
  llvm.amdgcn.raw.buffer.load.format.d16
  llvm.amdgcn.struct.buffer.load
  llvm.amdgcn.struct.buffer.load.format
  llvm.amdgcn.struct.buffer.load.format.d16
  llvm.amdgcn.raw.buffer.store
  llvm.amdgcn.raw.buffer.store.format
  llvm.amdgcn.raw.buffer.store.format.d16
  llvm.amdgcn.struct.buffer.store
  llvm.amdgcn.struct.buffer.store.format
  llvm.amdgcn.struct.buffer.store.format.d16
  llvm.amdgcn.raw.buffer.atomic.*
  llvm.amdgcn.struct.buffer.atomic.*

with the following changes from the llvm.amdgcn.buffer.*
intrinsics:

- there are separate raw and struct versions: raw does not have an index arg and sets idxen=0 in the instruction, and struct always sets idxen=1 in the instruction even if the index is 0, to allow for the fact that gfx9 does bounds checking differently depending on whether idxen is set;

- there is a combined cachepolicy arg (glc+slc)

- there are now only two offset args: one for the offset that is included in bounds checking and swizzling, to be split between the instruction's voffset and immoffset fields, and one for the offset that is excluded from bounds checking and swizzling, to go into the instruction's soffset field.

The AMDISD::BUFFER_* SD nodes always have an index operand, all three
offset operands, combined cachepolicy operand, and an extra idxen
operand.

The obsolescent llvm.amdgcn.buffer.* intrinsics continue to work.

Change-Id: If897ea7dc34fcbf4d5496e98cc99a934f62fc205


Repository:
  rL LLVM

https://reviews.llvm.org/D50306

Files:
  include/llvm/IR/IntrinsicsAMDGPU.td
  lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  lib/Target/AMDGPU/BUFInstructions.td
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIISelLowering.h
  lib/Target/AMDGPU/SIInstrInfo.td
  lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
  test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.atomic.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.d16.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.format.d16.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.format.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.store.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.atomic.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.d16.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.d16.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.format.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.store.ll

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