[PATCH] D50004: [PowerPC] Emit xscpsgndp instead of xxlor when copying floating point scalar registers for P9

[Jinsong Ji via Phabricator via llvm-commits]

jsji added a comment.

In https://reviews.llvm.org/D50004#1185846, @inouehrs wrote:

> > Does the comment about normalization only pertain to ISA 2.07?
>
> As I browse the document, neither ISA 2.07 nor 3.0 mention about normalization by xscpsgndp.
>  https://reviews.llvm.org/P8 UM says xscpsgndp, xvcpsgndp and fmr are normalizing instruction. https://reviews.llvm.org/P9 UM say nothing.
>  Since fmr is also a normalizing instruction, I feel it is acceptable to use xscpsgndp for coping register.


https://reviews.llvm.org/P9 UM does clarified the difference:

4.3.6 Handling of Denormal Single-Precision Values in Double-Precision Format
Unlike previous generation processors, such as the POWER8 processor, **the POWER9 processor is capable of handling denormal single-precision values as inputs for all subsequent instructions.** Whereas, in some cases, the POWER8 processor takes a soft-patch interrupt to allow the interrupt handler to reformat the input operands to a double-precision format and then re-execute the instruction, the POWER9 processor simply executes normally regardless of how that number was produced.


https://reviews.llvm.org/D50004