[llvm] r338784 - [AMDGPU] Minor change to d16 buffer load implementation
Tim Renouf via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 2 16:33:01 PDT 2018
Author: tpr
Date: Thu Aug 2 16:33:01 2018
New Revision: 338784
URL: http://llvm.org/viewvc/llvm-project?rev=338784&view=rev
Log:
[AMDGPU] Minor change to d16 buffer load implementation
Summary:
By not reconstructing the operand list of the SDNode, this change makes
it easier to add the forthcoming new tbuffer and buffer intrinsics.
Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D49995
Change-Id: I0cb79ef0801532645d7dd954a6d7355139db7b38
Modified:
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=338784&r1=338783&r2=338784&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Thu Aug 2 16:33:01 2018
@@ -3627,18 +3627,9 @@ static SDValue adjustLoadValueTypeImpl(S
SDValue SITargetLowering::adjustLoadValueType(unsigned Opcode,
MemSDNode *M,
SelectionDAG &DAG,
+ ArrayRef<SDValue> Ops,
bool IsIntrinsic) const {
SDLoc DL(M);
- SmallVector<SDValue, 10> Ops;
- Ops.reserve(M->getNumOperands());
-
- Ops.push_back(M->getOperand(0));
- if (IsIntrinsic)
- Ops.push_back(DAG.getConstant(Opcode, DL, MVT::i32));
-
- // Skip 1, as it is the intrinsic ID.
- for (unsigned I = 2, E = M->getNumOperands(); I != E; ++I)
- Ops.push_back(M->getOperand(I));
bool Unpacked = Subtarget->hasUnpackedD16VMem();
EVT LoadVT = M->getValueType(0);
@@ -5099,20 +5090,16 @@ SDValue SITargetLowering::LowerINTRINSIC
EVT IntVT = VT.changeTypeToInteger();
auto *M = cast<MemSDNode>(Op);
EVT LoadVT = Op.getValueType();
- bool IsD16 = LoadVT.getScalarType() == MVT::f16;
- if (IsD16)
- return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16, M, DAG);
+ if (LoadVT.getScalarType() == MVT::f16)
+ return adjustLoadValueType(AMDGPUISD::BUFFER_LOAD_FORMAT_D16,
+ M, DAG, Ops);
return DAG.getMemIntrinsicNode(Opc, DL, Op->getVTList(), Ops, IntVT,
M->getMemOperand());
}
case Intrinsic::amdgcn_tbuffer_load: {
MemSDNode *M = cast<MemSDNode>(Op);
EVT LoadVT = Op.getValueType();
- bool IsD16 = LoadVT.getScalarType() == MVT::f16;
- if (IsD16) {
- return adjustLoadValueType(AMDGPUISD::TBUFFER_LOAD_FORMAT_D16, M, DAG);
- }
SDValue Ops[] = {
Op.getOperand(0), // Chain
@@ -5127,6 +5114,9 @@ SDValue SITargetLowering::LowerINTRINSIC
Op.getOperand(10) // slc
};
+ if (LoadVT.getScalarType() == MVT::f16)
+ return adjustLoadValueType(AMDGPUISD::TBUFFER_LOAD_FORMAT_D16,
+ M, DAG, Ops);
return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_LOAD_FORMAT, DL,
Op->getVTList(), Ops, LoadVT,
M->getMemOperand());
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h?rev=338784&r1=338783&r2=338784&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h Thu Aug 2 16:33:01 2018
@@ -81,7 +81,7 @@ private:
SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
SDValue adjustLoadValueType(unsigned Opcode, MemSDNode *M,
- SelectionDAG &DAG,
+ SelectionDAG &DAG, ArrayRef<SDValue> Ops,
bool IsIntrinsic = false) const;
SDValue handleD16VData(SDValue VData, SelectionDAG &DAG) const;
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