[PATCH] D50079: [ARM] arm.assert.zeroext intrinsics

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> Add to BitCode/compatibility-6.0.ll test and just keep this codegen one too?

Yes, that's probably enough for basic testing...

But a portable intrinsic probably also needs to go through a design discussion on llvmdev, so it's clear this is the right design: how is this different from other similar constructs like !range metadata and llvm.assert, is there some way to communicate this information to SelectionDAG in some way that doesn't involve mutating the IR, how can we generalize this, etc.

Or maybe we could keep this target-specific, with a different name, with the justification that this isn't really an IR extension, just an implementation detail of the code generator to work around SelectionDAG limitations.  We already have a sort of notion that when IR is passed to the code generator, the code generator can modify IR in ways that might not make sense to general IR passes.   For example, llvm.ppc.mtctr is an intrinsic only used by PPCCTRLoops.  But in that case we should use a name that makes it clear it isn't a general-purpose intrinsic usable by frontends or IR optimizations.


https://reviews.llvm.org/D50079