[llvm] r338584 - [llvm-mca][x86] Add PREFETCHW instruction resource tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 1 09:34:39 PDT 2018
Author: rksimon
Date: Wed Aug 1 09:34:39 2018
New Revision: 338584
URL: http://llvm.org/viewvc/llvm-project?rev=338584&view=rev
Log:
[llvm-mca][x86] Add PREFETCHW instruction resource tests
These aren't just available via 3DNow! so test for them separately as well.
Added:
llvm/trunk/test/tools/llvm-mca/X86/Broadwell/resources-prefetchw.s
llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-prefetchw.s
llvm/trunk/test/tools/llvm-mca/X86/Generic/resources-prefetchw.s
llvm/trunk/test/tools/llvm-mca/X86/SLM/resources-prefetchw.s
llvm/trunk/test/tools/llvm-mca/X86/SkylakeClient/resources-prefetchw.s
llvm/trunk/test/tools/llvm-mca/X86/SkylakeServer/resources-prefetchw.s
llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-prefetchw.s
Added: llvm/trunk/test/tools/llvm-mca/X86/Broadwell/resources-prefetchw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/Broadwell/resources-prefetchw.s?rev=338584&view=auto
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/Broadwell/resources-prefetchw.s (added)
+++ llvm/trunk/test/tools/llvm-mca/X86/Broadwell/resources-prefetchw.s Wed Aug 1 09:34:39 2018
@@ -0,0 +1,38 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=broadwell -instruction-tables < %s | FileCheck %s
+
+prefetch (%rax)
+prefetchw (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 5 0.50 * * prefetch (%rax)
+# CHECK-NEXT: 1 5 0.50 * * prefetchw (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - BWDivider
+# CHECK-NEXT: [1] - BWFPDivider
+# CHECK-NEXT: [2] - BWPort0
+# CHECK-NEXT: [3] - BWPort1
+# CHECK-NEXT: [4] - BWPort2
+# CHECK-NEXT: [5] - BWPort3
+# CHECK-NEXT: [6] - BWPort4
+# CHECK-NEXT: [7] - BWPort5
+# CHECK-NEXT: [8] - BWPort6
+# CHECK-NEXT: [9] - BWPort7
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
+# CHECK-NEXT: - - - - 1.00 1.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - prefetch (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - prefetchw (%rax)
Added: llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-prefetchw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-prefetchw.s?rev=338584&view=auto
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-prefetchw.s (added)
+++ llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-prefetchw.s Wed Aug 1 09:34:39 2018
@@ -0,0 +1,42 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -instruction-tables < %s | FileCheck %s
+
+prefetch (%rax)
+prefetchw (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 5 1.00 * * prefetch (%rax)
+# CHECK-NEXT: 1 5 1.00 * * prefetchw (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - JALU0
+# CHECK-NEXT: [1] - JALU1
+# CHECK-NEXT: [2] - JDiv
+# CHECK-NEXT: [3] - JFPA
+# CHECK-NEXT: [4] - JFPM
+# CHECK-NEXT: [5] - JFPU0
+# CHECK-NEXT: [6] - JFPU1
+# CHECK-NEXT: [7] - JLAGU
+# CHECK-NEXT: [8] - JMul
+# CHECK-NEXT: [9] - JSAGU
+# CHECK-NEXT: [10] - JSTC
+# CHECK-NEXT: [11] - JVALU0
+# CHECK-NEXT: [12] - JVALU1
+# CHECK-NEXT: [13] - JVIMUL
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
+# CHECK-NEXT: - - - - - - - 2.00 - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] Instructions:
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - prefetch (%rax)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - prefetchw (%rax)
Added: llvm/trunk/test/tools/llvm-mca/X86/Generic/resources-prefetchw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/Generic/resources-prefetchw.s?rev=338584&view=auto
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/Generic/resources-prefetchw.s (added)
+++ llvm/trunk/test/tools/llvm-mca/X86/Generic/resources-prefetchw.s Wed Aug 1 09:34:39 2018
@@ -0,0 +1,36 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -instruction-tables < %s | FileCheck %s
+
+prefetch (%rax)
+prefetchw (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 5 0.50 * * prefetch (%rax)
+# CHECK-NEXT: 1 5 0.50 * * prefetchw (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SBDivider
+# CHECK-NEXT: [1] - SBFPDivider
+# CHECK-NEXT: [2] - SBPort0
+# CHECK-NEXT: [3] - SBPort1
+# CHECK-NEXT: [4] - SBPort4
+# CHECK-NEXT: [5] - SBPort5
+# CHECK-NEXT: [6.0] - SBPort23
+# CHECK-NEXT: [6.1] - SBPort23
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1]
+# CHECK-NEXT: - - - - - - 1.00 1.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
+# CHECK-NEXT: - - - - - - 0.50 0.50 prefetch (%rax)
+# CHECK-NEXT: - - - - - - 0.50 0.50 prefetchw (%rax)
Added: llvm/trunk/test/tools/llvm-mca/X86/SLM/resources-prefetchw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/SLM/resources-prefetchw.s?rev=338584&view=auto
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/SLM/resources-prefetchw.s (added)
+++ llvm/trunk/test/tools/llvm-mca/X86/SLM/resources-prefetchw.s Wed Aug 1 09:34:39 2018
@@ -0,0 +1,36 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=slm -instruction-tables < %s | FileCheck %s
+
+prefetch (%rax)
+prefetchw (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 * * prefetch (%rax)
+# CHECK-NEXT: 1 3 1.00 * * prefetchw (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SLMDivider
+# CHECK-NEXT: [1] - SLMFPDivider
+# CHECK-NEXT: [2] - SLMFPMultiplier
+# CHECK-NEXT: [3] - SLM_FPC_RSV0
+# CHECK-NEXT: [4] - SLM_FPC_RSV1
+# CHECK-NEXT: [5] - SLM_IEC_RSV0
+# CHECK-NEXT: [6] - SLM_IEC_RSV1
+# CHECK-NEXT: [7] - SLM_MEC_RSV
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
+# CHECK-NEXT: - - - - - - - 2.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
+# CHECK-NEXT: - - - - - - - 1.00 prefetch (%rax)
+# CHECK-NEXT: - - - - - - - 1.00 prefetchw (%rax)
Added: llvm/trunk/test/tools/llvm-mca/X86/SkylakeClient/resources-prefetchw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/SkylakeClient/resources-prefetchw.s?rev=338584&view=auto
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/SkylakeClient/resources-prefetchw.s (added)
+++ llvm/trunk/test/tools/llvm-mca/X86/SkylakeClient/resources-prefetchw.s Wed Aug 1 09:34:39 2018
@@ -0,0 +1,38 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake -instruction-tables < %s | FileCheck %s
+
+prefetch (%rax)
+prefetchw (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 5 0.50 * * prefetch (%rax)
+# CHECK-NEXT: 1 5 0.50 * * prefetchw (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SKLDivider
+# CHECK-NEXT: [1] - SKLFPDivider
+# CHECK-NEXT: [2] - SKLPort0
+# CHECK-NEXT: [3] - SKLPort1
+# CHECK-NEXT: [4] - SKLPort2
+# CHECK-NEXT: [5] - SKLPort3
+# CHECK-NEXT: [6] - SKLPort4
+# CHECK-NEXT: [7] - SKLPort5
+# CHECK-NEXT: [8] - SKLPort6
+# CHECK-NEXT: [9] - SKLPort7
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
+# CHECK-NEXT: - - - - 1.00 1.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - prefetch (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - prefetchw (%rax)
Added: llvm/trunk/test/tools/llvm-mca/X86/SkylakeServer/resources-prefetchw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/SkylakeServer/resources-prefetchw.s?rev=338584&view=auto
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/SkylakeServer/resources-prefetchw.s (added)
+++ llvm/trunk/test/tools/llvm-mca/X86/SkylakeServer/resources-prefetchw.s Wed Aug 1 09:34:39 2018
@@ -0,0 +1,38 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512 -instruction-tables < %s | FileCheck %s
+
+prefetch (%rax)
+prefetchw (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 5 0.50 * * prefetch (%rax)
+# CHECK-NEXT: 1 5 0.50 * * prefetchw (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SKXDivider
+# CHECK-NEXT: [1] - SKXFPDivider
+# CHECK-NEXT: [2] - SKXPort0
+# CHECK-NEXT: [3] - SKXPort1
+# CHECK-NEXT: [4] - SKXPort2
+# CHECK-NEXT: [5] - SKXPort3
+# CHECK-NEXT: [6] - SKXPort4
+# CHECK-NEXT: [7] - SKXPort5
+# CHECK-NEXT: [8] - SKXPort6
+# CHECK-NEXT: [9] - SKXPort7
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
+# CHECK-NEXT: - - - - 1.00 1.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - prefetch (%rax)
+# CHECK-NEXT: - - - - 0.50 0.50 - - - - prefetchw (%rax)
Added: llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-prefetchw.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-prefetchw.s?rev=338584&view=auto
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-prefetchw.s (added)
+++ llvm/trunk/test/tools/llvm-mca/X86/Znver1/resources-prefetchw.s Wed Aug 1 09:34:39 2018
@@ -0,0 +1,40 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -instruction-tables < %s | FileCheck %s
+
+prefetch (%rax)
+prefetchw (%rax)
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 8 0.50 * * prefetch (%rax)
+# CHECK-NEXT: 1 8 0.50 * * prefetchw (%rax)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - ZnAGU0
+# CHECK-NEXT: [1] - ZnAGU1
+# CHECK-NEXT: [2] - ZnALU0
+# CHECK-NEXT: [3] - ZnALU1
+# CHECK-NEXT: [4] - ZnALU2
+# CHECK-NEXT: [5] - ZnALU3
+# CHECK-NEXT: [6] - ZnDivider
+# CHECK-NEXT: [7] - ZnFPU0
+# CHECK-NEXT: [8] - ZnFPU1
+# CHECK-NEXT: [9] - ZnFPU2
+# CHECK-NEXT: [10] - ZnFPU3
+# CHECK-NEXT: [11] - ZnMultiplier
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - prefetch (%rax)
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - prefetchw (%rax)
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