[PATCH] D50030: [ARM] Adjust AND immediates to make them cheaper to select.

[Sam Parker via Phabricator via llvm-commits]

samparker added inline comments.


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Comment at: test/CodeGen/ARM/Windows/vla.ll:17
 ; CHECK-SMALL-CODE:   adds [[R4:r[0-9]+]], #7
-; CHECK-SMALL-CODE:   bic [[R4]], [[R4]], #7
+; CHECK-SMALL-CODE:   bic [[R4]], [[R4]], #4
 ; CHECK-SMALL-CODE:   lsrs r4, [[R4]], #2
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efriedma wrote:
> samparker wrote:
> > Just a bug in the existing test case?
> The new transform prefers the immediate ~4 over the immediate ~7 because it has more bits set.  They're equivalent here because the two low bits get shifted out anyway.  Maybe the transform should be adjusted to prefer ~7?
Using the smaller immediate sounds fine to me, especially for T1. Some tests for using BIC instead of an AND with a const pool load would be good.


Repository:
  rL LLVM

https://reviews.llvm.org/D50030