[PATCH] D50046: [RISCV] Add InstAlias definitions for add, and, xor, or, sll, srl, sra, slt and sltu with immediate

Kito Cheng via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jul 31 18:34:15 PDT 2018


kito-cheng added inline comments.


================
Comment at: test/MC/RISCV/rvi-aliases-valid.s:179
+
+# CHECK-INST: srli a2, a3, 4
+# CHECK-ALIAS: srli a2, a3, 4
----------------
sabuasal wrote:
> This test should print the canonical version of the instruction, you are printing the Alias. 
Those alias instructions always disassemble to **i** version in GAS even -M no-aliases is given, my thought is keep the behavior with GAS.


https://reviews.llvm.org/D50046





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