[PATCH] D50096: [SystemZ, TableGen] Fix shift count handling

[Ulrich Weigand via Phabricator via llvm-commits]

uweigand created this revision.
uweigand added reviewers: efriedma, cuviper, tstellar, jonpa.
Herald added a subscriber: llvm-commits.

As noticed in https://reviews.llvm.org/D50018, the DAG combiner logic to simplify AND masks in shift counts are invalid.

While it is true that the SystemZ shift instructions ignore all but the low 6 bits of the shift count, it is still invalid to simplify the AND masks while the DAG still uses the standard shift operators (which are *not* defined to match the SystemZ instruction behavior).

Instead, this patch performs equivalent operations during instruction selection.  For completely removing the AND, this now happens via additional DAG match patterns implemented by a multi-alternative PatFrags.  For simplifying a 32-bit AND to a 16-bit AND, the existing DAG patterns were already mostly OK, they just needed an output XForm to actually truncate the immediate value.

Unfortunately, the latter change also exposed a bug in TableGen: it seems XForms are currently only handled correctly for direct operands of the outermost operation node.  This patch also fixes that bug by simply recurring through the whole pattern.


Repository:
  rL LLVM

https://reviews.llvm.org/D50096

Files:
  lib/Target/SystemZ/SystemZISelLowering.cpp
  lib/Target/SystemZ/SystemZISelLowering.h
  lib/Target/SystemZ/SystemZInstrInfo.td
  lib/Target/SystemZ/SystemZOperands.td
  lib/Target/SystemZ/SystemZOperators.td
  test/CodeGen/SystemZ/shift-12.ll
  utils/TableGen/CodeGenDAGPatterns.cpp

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