[PATCH] D50046: [RISCV] Add InstAlias definitions for add, and, xor, or, sll, srl, sra, slt and sltu with immediate

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng updated this revision to Diff 158200.
kito-cheng added a comment.

Update testcase.


https://reviews.llvm.org/D50046

Files:
  lib/Target/RISCV/RISCVInstrInfo.td
  test/MC/RISCV/rvi-aliases-valid.s


Index: test/MC/RISCV/rvi-aliases-valid.s
===================================================================
--- test/MC/RISCV/rvi-aliases-valid.s
+++ test/MC/RISCV/rvi-aliases-valid.s
@@ -155,3 +155,39 @@
 # CHECK-INST: sfence.vma a0, zero
 # CHECK-ALIAS: sfence.vma a0
 sfence.vma a0
+
+# CHECK-INST: addi a2, a3, 4
+# CHECK-ALIAS: addi a2, a3, 4
+add a2,a3,4
+
+# CHECK-INST: andi a2, a3, 4
+# CHECK-ALIAS: andi a2, a3, 4
+and a2,a3,4
+
+# CHECK-INST: xori a2, a3, 4
+# CHECK-ALIAS: xori a2, a3, 4
+xor a2,a3,4
+
+# CHECK-INST: ori a2, a3, 4
+# CHECK-ALIAS: ori a2, a3, 4
+or a2,a3,4
+
+# CHECK-INST: slli a2, a3, 4
+# CHECK-ALIAS: slli a2, a3, 4
+sll a2,a3,4
+
+# CHECK-INST: srli a2, a3, 4
+# CHECK-ALIAS: srli a2, a3, 4
+srl a2,a3,4
+
+# CHECK-INST: srai a2, a3, 4
+# CHECK-ALIAS: srai a2, a3, 4
+sra a2,a3,4
+
+# CHECK-INST: slti a2, a3, 4
+# CHECK-ALIAS: slti a2, a3, 4
+slt a2,a3,4
+
+# CHECK-INST: sltiu a2, a3, 4
+# CHECK-ALIAS: sltiu a2, a3, 4
+sltu a2,a3,4
Index: lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- lib/Target/RISCV/RISCVInstrInfo.td
+++ lib/Target/RISCV/RISCVInstrInfo.td
@@ -550,6 +550,27 @@
 def : InstAlias<"sfence.vma",     (SFENCE_VMA      X0, X0)>;
 def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;
 
+let EmitPriority = 0 in {
+def : InstAlias<"add $rd, $rs1, $imm12",
+                (ADDI  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"and $rd, $rs1, $imm12",
+                (ANDI  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"xor $rd, $rs1, $imm12",
+                (XORI  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"or $rd, $rs1, $imm12",
+                (ORI  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"sll $rd, $rs1, $imm12",
+                (SLLI  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"srl $rd, $rs1, $imm12",
+                (SRLI  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"sra $rd, $rs1, $imm12",
+                (SRAI  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"slt $rd, $rs1, $imm12",
+                (SLTI  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+def : InstAlias<"sltu $rd, $rs1, $imm12",
+                (SLTIU  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
+}
+
 //===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns
 //


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D50046.158200.patch
Type: text/x-patch
Size: 2386 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180731/524ea19d/attachment.bin>