[PATCH] D50030: [ARM] Adjust AND immediates to make them cheaper to select.

[Eli Friedman via Phabricator via llvm-commits]

efriedma created this revision.
efriedma added reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover.
Herald added a reviewer: javed.absar.
Herald added subscribers: chrib, kristof.beyls.

LLVM normally prefers to minimize the number of bits set in an AND immediate, but that doesn't always match the available ARM instructions.    In Thumb1 mode, prefer uxtb or uxth where possible; otherwise, prefer a two-instruction sequence movs+ands or movs+bics where possible.

Some potential improvements outlined in ARMTargetLowering::targetShrinkDemandedConstant, but seems to work pretty well already.

The ARMISelDAGToDAG fix ensures we don't generate an invalid UBFX instruction due to a larger-than-expected mask. (It's orthogonal, in some sense, but as far as I can tell it's either impossible or nearly impossible to reproduce the bug without this change.)

According to my testing, this seems to consistently improve codesize by a small amount by forming bic more often for ISD::AND with an immediate.


Repository:
  rL LLVM

https://reviews.llvm.org/D50030

Files:
  lib/Target/ARM/ARMISelDAGToDAG.cpp
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMISelLowering.h
  test/CodeGen/ARM/Windows/alloca.ll
  test/CodeGen/ARM/Windows/vla.ll
  test/CodeGen/ARM/and-cmpz.ll
  test/CodeGen/ARM/illegal-bitfield-loadstore.ll
  test/CodeGen/ARM/select_const.ll

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