[PATCH] D50018: SystemZ: keep AND masks before SHL i128

[Josh Stone via Phabricator via llvm-commits]

cuviper created this revision.
cuviper added reviewers: uweigand, colpell.
Herald added a subscriber: llvm-commits.

SystemZ normally tries to combine away AND masks for the lower bits of a shift operand, as it only uses the least 6 bits anyway.  This is fine for native integers <= 64 bits, but it leads to bad results when shifting i128, as the builtin `__ashlti3` needs the operand to remain masked.


Repository:
  rL LLVM

https://reviews.llvm.org/D50018

Files:
  lib/Target/SystemZ/SystemZISelLowering.cpp
  test/CodeGen/SystemZ/shift-12.ll


Index: test/CodeGen/SystemZ/shift-12.ll
===================================================================
--- test/CodeGen/SystemZ/shift-12.ll
+++ test/CodeGen/SystemZ/shift-12.ll
@@ -104,3 +104,14 @@
   %reuse = add i32 %and, %shift
   ret i32 %reuse
 }
+
+; Test that AND is not removed for i128 (which calls __ashlti3)
+define i128 @f11(i128 %a, i32 %sh) {
+; CHECK-LABEL: f11:
+; CHECK: risbg %r4, %r4, 57, 191, 0
+; CHECK: brasl %r14, __ashlti3 at PLT
+  %and = and i32 %sh, 127
+  %ext = zext i32 %and to i128
+  %shift = shl i128 %a, %ext
+  ret i128 %shift
+}
Index: lib/Target/SystemZ/SystemZISelLowering.cpp
===================================================================
--- lib/Target/SystemZ/SystemZISelLowering.cpp
+++ lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -5537,8 +5537,9 @@
   // entirely, but we can still truncate it to a 16-bit value. This prevents
   // us from ending up with a NILL with a signed operand, which will cause the
   // instruction printer to abort.
+  EVT VT = N->getValueType(0);
   SDValue N1 = N->getOperand(1);
-  if (N1.getOpcode() == ISD::AND) {
+  if (N1.getOpcode() == ISD::AND && VT.getScalarSizeInBits() <= 64) {
     SDValue AndMaskOp = N1->getOperand(1);
     auto *AndMask = dyn_cast<ConstantSDNode>(AndMaskOp);
 


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