[PATCH] D49924: [DAGCombiner] transform sub-of-shifted-signbit to add

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In https://reviews.llvm.org/D49924#1180892, @efriedma wrote:

> Yes, the AArch64 issue is that we decide to use add-with-immediate rather than sub-with-shifted-operand.  Which form is better probably depends on the CPU and the context: by itself, on an A57 you're trading an expensive instruction for cheaper instruction, but if the immediate can be hoisted out of a hot loop the expensive instruction might be cheaper than two cheap instructions.  But I think the sub-with-shifted-operand might be cheaper on other CPUs?
>
> Anyway, that's basically independent of this patch, so don't worry about it.


Thanks!


https://reviews.llvm.org/D49924