[PATCH] D38128: Handle COPYs of physregs better (regalloc hints)
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 30 11:51:00 PDT 2018
RKSimon added inline comments.
================
Comment at: test/CodeGen/X86/vector-shift-ashr-128.ll:270
; SSE41: # %bb.0:
-; SSE41-NEXT: movdqa %xmm0, %xmm2
-; SSE41-NEXT: movdqa %xmm1, %xmm0
+; SSE41-NEXT: movdqa %xmm1, %xmm2
+; SSE41-NEXT: movdqa %xmm0, %xmm1
----------------
niravd wrote:
> All of the SSE4 changes regarding shifts seem to generate unnecessary register shuffling.
If I had to guess - this is probably due to SSE41's PBLENDV instructions being hardwired to use xmm0
Repository:
rL LLVM
https://reviews.llvm.org/D38128
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