[PATCH] D49994: Allow constraining virtual register's class within reason

[Alexey Zhikhartsev via Phabricator via llvm-commits]

alexey.zhikhar created this revision.
alexey.zhikhar added reviewers: uweigand, efriedma, bogner.
Herald added a subscriber: llvm-commits.

At the very end of instruction selection, in `InstrEmitter`, handle overlapping register classes to eliminate redundant copy instructions.

Given the following code:

  a = def
  c = CopyToReg a

The current implementation of `InstrEmitter` checks whether `a` and `c` belong to the same register class, and, if so, coalesces CopyToReg away:

  a = def
  c = CopyToReg a
      =>
  c = def

In pseudocode, the algorithm can be expressed as

  if RegClass(c) == RegClass(a):
      make it "c = def"

However, in a case where register classes are not exactly equal but overlap, the CopyToReg is not eliminated. This patch checks whether two register classes overlap and the number of registers in the overlap is greater than `MinRCSize`.       ↪ In pseudocode:

  if |RegClass(c) ∩ RegClass(a)| ≥ MinRCSize:
      make it "c = def"

Corresponding discussion on llvm-dev:

http://lists.llvm.org/pipermail/llvm-dev/2018-May/123663.html
https://groups.google.com/forum/#!topic/llvm-dev/BHFhRkYY2ng

Credit for this patch goes to Ulrich Weigand.


Repository:
  rL LLVM

https://reviews.llvm.org/D49994

Files:
  lib/CodeGen/SelectionDAG/InstrEmitter.cpp


Index: lib/CodeGen/SelectionDAG/InstrEmitter.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -248,8 +248,11 @@
             User->getOperand(2).getResNo() == i) {
           unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
           if (TargetRegisterInfo::isVirtualRegister(Reg)) {
-            const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
-            if (RegRC == RC) {
+            // Allow constraining the virtual register's class within reason,
+            // just like what AddRegisterOperand will allow.
+            const TargetRegisterClass *ConstrainedRC
+              = MRI->constrainRegClass(Reg, RC, MinRCSize);
+            if (ConstrainedRC) {
               VRBase = Reg;
               MIB.addReg(VRBase, RegState::Define);
               break;


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