[PATCH] D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms.

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb updated this revision to Diff 157958.
andreadb added a comment.

Patch rebased and updated.

To answe to Roman's questions:
I verified that the patch works as intended for zero latency instructions that are not marked as "dependency breaking".
If a zero-latency instruction reads a register, then it has to wait on the input. If it is marked as dep-breaking, then it can issue immediately.
If a zero-latency is not marked dep-breaking, and the inputs are all ready, then it can be issued immediately.

As I wrote in a previous comment, we can have a follow-up patch where we teach to tablegen how to generate the body of `isDependencyBreaking` predicate for us (and potentially expose that same logic to TargetInstrInfo).


https://reviews.llvm.org/D49310

Files:
  include/llvm/MC/MCInstrAnalysis.h
  lib/MC/MCInstrAnalysis.cpp
  lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
  test/tools/llvm-mca/X86/BtVer2/dependency-breaking-cmp.s
  test/tools/llvm-mca/X86/BtVer2/dependency-breaking-pcmpeq.s
  test/tools/llvm-mca/X86/BtVer2/dependency-breaking-sbb-2.s
  test/tools/llvm-mca/X86/BtVer2/one-idioms.s
  tools/llvm-mca/DispatchStage.cpp
  tools/llvm-mca/InstrBuilder.cpp
  tools/llvm-mca/Instruction.h
  tools/llvm-mca/RetireStage.cpp

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