[llvm] r338205 - [SelectionDAG] Pass std::vector by reference instead of by pointer to BuildSDIV/BuildUDIV.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 28 12:44:20 PDT 2018
Author: ctopper
Date: Sat Jul 28 12:44:20 2018
New Revision: 338205
URL: http://llvm.org/viewvc/llvm-project?rev=338205&view=rev
Log:
[SelectionDAG] Pass std::vector by reference instead of by pointer to BuildSDIV/BuildUDIV.
This removes the need for an assert to ensure the pointer isn't null.
Years ago we had ifs the checked the pointer was non-null before very access to the vector. These checks were removed and replaced with a single assert. But a reference seems more suitable here.
Modified:
llvm/trunk/include/llvm/CodeGen/TargetLowering.h
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Modified: llvm/trunk/include/llvm/CodeGen/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetLowering.h?rev=338205&r1=338204&r2=338205&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetLowering.h Sat Jul 28 12:44:20 2018
@@ -3490,10 +3490,10 @@ public:
//
SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
bool IsAfterLegalization,
- std::vector<SDNode *> *Created) const;
+ std::vector<SDNode *> &Created) const;
SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
bool IsAfterLegalization,
- std::vector<SDNode *> *Created) const;
+ std::vector<SDNode *> &Created) const;
/// Targets may override this function to provide custom SDIV lowering for
/// power-of-2 denominators. If the target returns an empty SDValue, LLVM
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=338205&r1=338204&r2=338205&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Jul 28 12:44:20 2018
@@ -17921,7 +17921,7 @@ SDValue DAGCombiner::BuildSDIV(SDNode *N
std::vector<SDNode *> Built;
SDValue S =
- TLI.BuildSDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
+ TLI.BuildSDIV(N, C->getAPIntValue(), DAG, LegalOperations, Built);
for (SDNode *N : Built)
AddToWorklist(N);
@@ -17967,7 +17967,7 @@ SDValue DAGCombiner::BuildUDIV(SDNode *N
std::vector<SDNode *> Built;
SDValue S =
- TLI.BuildUDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
+ TLI.BuildUDIV(N, C->getAPIntValue(), DAG, LegalOperations, Built);
for (SDNode *N : Built)
AddToWorklist(N);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=338205&r1=338204&r2=338205&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sat Jul 28 12:44:20 2018
@@ -3465,9 +3465,7 @@ SDValue TargetLowering::BuildSDIVPow2(SD
/// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
SDValue TargetLowering::BuildSDIV(SDNode *N, const APInt &Divisor,
SelectionDAG &DAG, bool IsAfterLegalization,
- std::vector<SDNode *> *Created) const {
- assert(Created && "No vector to hold sdiv ops.");
-
+ std::vector<SDNode *> &Created) const {
EVT VT = N->getValueType(0);
SDLoc dl(N);
@@ -3478,7 +3476,7 @@ SDValue TargetLowering::BuildSDIV(SDNode
// If the sdiv has an 'exact' bit we can use a simpler lowering.
if (N->getFlags().hasExact())
- return BuildExactSDIV(*this, N->getOperand(0), Divisor, dl, DAG, *Created);
+ return BuildExactSDIV(*this, N->getOperand(0), Divisor, dl, DAG, Created);
APInt::ms magics = Divisor.magic();
@@ -3499,12 +3497,12 @@ SDValue TargetLowering::BuildSDIV(SDNode
// If d > 0 and m < 0, add the numerator
if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
- Created->push_back(Q.getNode());
+ Created.push_back(Q.getNode());
}
// If d < 0 and m > 0, subtract the numerator.
if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
- Created->push_back(Q.getNode());
+ Created.push_back(Q.getNode());
}
auto &DL = DAG.getDataLayout();
// Shift right algebraic if shift value is nonzero
@@ -3512,14 +3510,14 @@ SDValue TargetLowering::BuildSDIV(SDNode
Q = DAG.getNode(
ISD::SRA, dl, VT, Q,
DAG.getConstant(magics.s, dl, getShiftAmountTy(Q.getValueType(), DL)));
- Created->push_back(Q.getNode());
+ Created.push_back(Q.getNode());
}
// Extract the sign bit and add it to the quotient
SDValue T =
DAG.getNode(ISD::SRL, dl, VT, Q,
DAG.getConstant(VT.getScalarSizeInBits() - 1, dl,
getShiftAmountTy(Q.getValueType(), DL)));
- Created->push_back(T.getNode());
+ Created.push_back(T.getNode());
return DAG.getNode(ISD::ADD, dl, VT, Q, T);
}
@@ -3529,9 +3527,7 @@ SDValue TargetLowering::BuildSDIV(SDNode
/// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor,
SelectionDAG &DAG, bool IsAfterLegalization,
- std::vector<SDNode *> *Created) const {
- assert(Created && "No vector to hold udiv ops.");
-
+ std::vector<SDNode *> &Created) const {
EVT VT = N->getValueType(0);
SDLoc dl(N);
auto &DL = DAG.getDataLayout();
@@ -3554,7 +3550,7 @@ SDValue TargetLowering::BuildUDIV(SDNode
Q = DAG.getNode(
ISD::SRL, dl, VT, Q,
DAG.getConstant(Shift, dl, getShiftAmountTy(Q.getValueType(), DL)));
- Created->push_back(Q.getNode());
+ Created.push_back(Q.getNode());
// Get magic number for the shifted divisor.
magics = Divisor.lshr(Shift).magicu(Shift);
@@ -3573,7 +3569,7 @@ SDValue TargetLowering::BuildUDIV(SDNode
else
return SDValue(); // No mulhu or equivalent
- Created->push_back(Q.getNode());
+ Created.push_back(Q.getNode());
if (magics.a == 0) {
assert(magics.s < Divisor.getBitWidth() &&
@@ -3583,13 +3579,13 @@ SDValue TargetLowering::BuildUDIV(SDNode
DAG.getConstant(magics.s, dl, getShiftAmountTy(Q.getValueType(), DL)));
} else {
SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
- Created->push_back(NPQ.getNode());
+ Created.push_back(NPQ.getNode());
NPQ = DAG.getNode(
ISD::SRL, dl, VT, NPQ,
DAG.getConstant(1, dl, getShiftAmountTy(NPQ.getValueType(), DL)));
- Created->push_back(NPQ.getNode());
+ Created.push_back(NPQ.getNode());
NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
- Created->push_back(NPQ.getNode());
+ Created.push_back(NPQ.getNode());
return DAG.getNode(
ISD::SRL, dl, VT, NPQ,
DAG.getConstant(magics.s - 1, dl,
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