[PATCH] D49861: [X86] Improved sched models for X86 XCHG*rr instructions

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

In general - looks good, assuming that after rebasing ontop of https://reviews.llvm.org/D49912 there are no regressions.
A few nits.
The SLM & btver2 - are those placeholders, or those are real values from agner?



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Comment at: lib/Target/X86/X86SchedHaswell.td:128
 defm : HWWriteResPair<WriteBSWAP64,[HWPort06, HWPort15], 2, [1,1], 2>;
+defm : X86WriteRes<WriteXCHG, [HWPort0156], 2, [3], 3>;
 
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Nit: align?


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Comment at: lib/Target/X86/X86SchedSkylakeClient.td:115
 defm : SKLWriteResPair<WriteBSWAP64,[SKLPort06, SKLPort15], 2, [1,1], 2>; //
+defm : X86WriteRes<WriteXCHG, [SKLPort0156], 2, [3], 3>;
 
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Nit: align?


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Comment at: lib/Target/X86/X86Schedule.td:123
 defm WriteBSWAP64: X86SchedWritePair; // Byte Order (Endiannes) Swap
+def  WriteXCHG   : SchedWrite;
 
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`// Exchange the contents of two operands`
?


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Comment at: lib/Target/X86/X86ScheduleBtVer2.td:173
 defm : JWriteResIntPair<WriteBSWAP64,[JALU01], 1>;
+defm : X86WriteRes<WriteXCHG,        [JALU01], 1, [1], 1>;
 
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These are from agner?


https://reviews.llvm.org/D49861