[PATCH] D49563: [ARM] Add new target feature to fuse literal generation

[Evandro Menezes via Phabricator via llvm-commits]

evandro added inline comments.


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Comment at: llvm/lib/Target/ARM/ARM.td:145
+// Fast execution of bottom and top halves of literal generation
+def FeatureFuseLiterals   : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true",
+                                             "CPU fuses literal generation operations">;
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fhahn wrote:
> evandro wrote:
> > fhahn wrote:
> > > FeatureFuseLiterals should be added to the cortex-a57 and cortex-a72 features according to the optimization guides. Can you also add a run lines with those CPUs to the test?
> > It's more complicated than that.  I had to enable `FeatureUseMISched` as well for this to be effective.  This is fine for Exynos, but it'd require more extensive testing on Cortex.
> Ah right! No worries then
Of course, Exynos needs this feature because there's no pipeline model for it in the ARM target.


Repository:
  rL LLVM

https://reviews.llvm.org/D49563