[llvm] r338107 - [InstSimplify] tests for D48828: fold extraction from std::pair
Hiroshi Inoue via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 27 00:21:03 PDT 2018
Author: inouehrs
Date: Fri Jul 27 00:21:02 2018
New Revision: 338107
URL: http://llvm.org/viewvc/llvm-project?rev=338107&view=rev
Log:
[InstSimplify] tests for D48828: fold extraction from std::pair
This commit includes unit tests for D48828, which enhances InstSimplify to enable jump threading with a method whose return type is std::pair<int, bool> or std::pair<bool, int>.
I am going to commit the actual transformation later.
Added:
llvm/trunk/test/Transforms/NewGVN/pair_jumpthread.ll
Modified:
llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll
llvm/trunk/test/Transforms/InstSimplify/shift.ll
Modified: llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll?rev=338107&r1=338106&r2=338107&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll (original)
+++ llvm/trunk/test/Transforms/InstSimplify/AndOrXor.ll Fri Jul 27 00:21:02 2018
@@ -964,3 +964,148 @@ define i32 @reversed_not(i32 %a) {
%or = or i32 %a, %nega
ret i32 %or
}
+
+define i64 @shl_or_and1(i32 %a, i1 %b) {
+; CHECK-LABEL: @shl_or_and1(
+; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[B:%.*]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 32
+; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 1
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %tmp1 = zext i32 %a to i64
+ %tmp2 = zext i1 %b to i64
+ %tmp3 = shl nuw i64 %tmp1, 32
+ %tmp4 = or i64 %tmp2, %tmp3
+ %tmp5 = and i64 %tmp4, 1
+ ret i64 %tmp5
+}
+
+define i64 @shl_or_and2(i32 %a, i1 %b) {
+; CHECK-LABEL: @shl_or_and2(
+; CHECK-NEXT: [[TMP1:%.*]] = zext i1 [[B:%.*]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[A:%.*]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 32
+; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4294967296
+; CHECK-NEXT: ret i64 [[TMP5]]
+;
+ %tmp1 = zext i1 %b to i64
+ %tmp2 = zext i32 %a to i64
+ %tmp3 = shl nuw i64 %tmp1, 32
+ %tmp4 = or i64 %tmp2, %tmp3
+ %tmp5 = and i64 %tmp4, 4294967296
+ ret i64 %tmp5
+}
+
+define i32 @shl_or_and3(i32 %a, i32 %b) {
+; concatinate two 32-bit integers and extract lower 32-bit
+; CHECK-LABEL: @shl_or_and3(
+; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 32
+; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4294967295
+; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
+; CHECK-NEXT: ret i32 [[TMP6]]
+;
+ %tmp1 = zext i32 %a to i64
+ %tmp2 = zext i32 %b to i64
+ %tmp3 = shl nuw i64 %tmp1, 32
+ %tmp4 = or i64 %tmp2, %tmp3
+ %tmp5 = and i64 %tmp4, 4294967295
+ %tmp6 = trunc i64 %tmp5 to i32
+ ret i32 %tmp6
+}
+
+define i32 @shl_or_and4(i16 %a, i16 %b) {
+; concatinate two 16-bit integers and extract higher 16-bit
+; CHECK-LABEL: @shl_or_and4(
+; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
+; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
+; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
+; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], -65536
+; CHECK-NEXT: ret i32 [[TMP5]]
+;
+ %tmp1 = zext i16 %a to i32
+ %tmp2 = zext i16 %b to i32
+ %tmp3 = shl nuw i32 %tmp1, 16
+ %tmp4 = or i32 %tmp2, %tmp3
+ %tmp5 = and i32 %tmp4, 4294901760 ; mask with 0xFFFF0000
+ ret i32 %tmp5
+}
+
+define i64 @shl_or_and5(i64 %a, i1 %b) {
+; CHECK-LABEL: @shl_or_and5(
+; CHECK-NEXT: [[TMP1:%.*]] = zext i64 [[A:%.*]] to i128
+; CHECK-NEXT: [[TMP2:%.*]] = zext i1 [[B:%.*]] to i128
+; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i128 [[TMP1]], 64
+; CHECK-NEXT: [[TMP4:%.*]] = or i128 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = and i128 [[TMP4]], 1
+; CHECK-NEXT: [[TMP6:%.*]] = trunc i128 [[TMP5]] to i64
+; CHECK-NEXT: ret i64 [[TMP6]]
+;
+ %tmp1 = zext i64 %a to i128
+ %tmp2 = zext i1 %b to i128
+ %tmp3 = shl nuw i128 %tmp1, 64
+ %tmp4 = or i128 %tmp2, %tmp3
+ %tmp5 = and i128 %tmp4, 1
+ %tmp6 = trunc i128 %tmp5 to i64
+ ret i64 %tmp6
+}
+
+define i32 @shl_or_and6(i16 %a, i16 %b) {
+; A variation of above test case, but fails due to the mask value
+; CHECK-LABEL: @shl_or_and6(
+; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
+; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
+; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
+; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], -65535
+; CHECK-NEXT: ret i32 [[TMP5]]
+;
+ %tmp1 = zext i16 %a to i32
+ %tmp2 = zext i16 %b to i32
+ %tmp3 = shl nuw i32 %tmp1, 16
+ %tmp4 = or i32 %tmp2, %tmp3
+ %tmp5 = and i32 %tmp4, 4294901761 ; mask with 0xFFFF0001
+ ret i32 %tmp5
+}
+
+define i32 @shl_or_and7(i16 %a, i16 %b) {
+; A variation of above test case, but fails due to the mask value
+; CHECK-LABEL: @shl_or_and7(
+; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
+; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
+; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
+; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], -131072
+; CHECK-NEXT: ret i32 [[TMP5]]
+;
+ %tmp1 = zext i16 %a to i32
+ %tmp2 = zext i16 %b to i32
+ %tmp3 = shl nuw i32 %tmp1, 16
+ %tmp4 = or i32 %tmp2, %tmp3
+ %tmp5 = and i32 %tmp4, 4294836224 ; mask with 0xFFFE0000
+ ret i32 %tmp5
+}
+
+define i32 @shl_or_and8(i16 %a, i16 %b) {
+; A variation of above test case, but fails due to the mask value
+; CHECK-LABEL: @shl_or_and8(
+; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[A:%.*]] to i32
+; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[B:%.*]] to i32
+; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i32 [[TMP1]], 16
+; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP4]], 131071
+; CHECK-NEXT: ret i32 [[TMP5]]
+;
+ %tmp1 = zext i16 %a to i32
+ %tmp2 = zext i16 %b to i32
+ %tmp3 = shl nuw i32 %tmp1, 16
+ %tmp4 = or i32 %tmp2, %tmp3
+ %tmp5 = and i32 %tmp4, 131071 ; mask with 0x1FFFF
+ ret i32 %tmp5
+}
Modified: llvm/trunk/test/Transforms/InstSimplify/shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/shift.ll?rev=338107&r1=338106&r2=338107&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/shift.ll (original)
+++ llvm/trunk/test/Transforms/InstSimplify/shift.ll Fri Jul 27 00:21:02 2018
@@ -175,3 +175,41 @@ define <2 x i8> @shl_by_sext_bool_vec(<2
ret <2 x i8> %r
}
+define i32 @shl_or_shr(i32 %a, i32 %b) {
+; CHECK-LABEL: @shl_or_shr(
+; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 32
+; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 32
+; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
+; CHECK-NEXT: ret i32 [[TMP6]]
+;
+ %tmp1 = zext i32 %a to i64
+ %tmp2 = zext i32 %b to i64
+ %tmp3 = shl nuw i64 %tmp1, 32
+ %tmp4 = or i64 %tmp2, %tmp3
+ %tmp5 = lshr i64 %tmp4, 32
+ %tmp6 = trunc i64 %tmp5 to i32
+ ret i32 %tmp6
+}
+
+define i32 @shl_or_shr2(i32 %a, i32 %b) {
+; Since shift count of shl is smaller than the size of %b, OR cannot be eliminated.
+; CHECK-LABEL: @shl_or_shr2(
+; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[A:%.*]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[B:%.*]] to i64
+; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP1]], 31
+; CHECK-NEXT: [[TMP4:%.*]] = or i64 [[TMP2]], [[TMP3]]
+; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 31
+; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
+; CHECK-NEXT: ret i32 [[TMP6]]
+;
+ %tmp1 = zext i32 %a to i64
+ %tmp2 = zext i32 %b to i64
+ %tmp3 = shl nuw i64 %tmp1, 31
+ %tmp4 = or i64 %tmp2, %tmp3
+ %tmp5 = lshr i64 %tmp4, 31
+ %tmp6 = trunc i64 %tmp5 to i32
+ ret i32 %tmp6
+}
Added: llvm/trunk/test/Transforms/NewGVN/pair_jumpthread.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/NewGVN/pair_jumpthread.ll?rev=338107&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/NewGVN/pair_jumpthread.ll (added)
+++ llvm/trunk/test/Transforms/NewGVN/pair_jumpthread.ll Fri Jul 27 00:21:02 2018
@@ -0,0 +1,122 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -newgvn -S | FileCheck %s
+; RUN: opt < %s -newgvn -jump-threading -S | FileCheck --check-prefix=CHECK-JT %s
+; This test is expected to fail until the transformation is committed.
+; XFAIL: *
+
+define signext i32 @testBI(i32 signext %v) {
+; Test with std::pair<bool, int>
+; based on the following C++ code
+; std::pair<bool, int> callee(int v) {
+; int a = dummy(v);
+; if (a) return std::make_pair(true, dummy(a));
+; else return std::make_pair(v < 0, v);
+; }
+; int func(int v) {
+; std::pair<bool, int> rc = callee(v);
+; if (rc.first) dummy(0);
+; return rc.second;
+; }
+; CHECK-LABEL: @testBI(
+; CHECK: _ZL6calleei.exit:
+; CHECK: [[PHIOFOPS:%.*]] = phi i64 [ 1, %if.then.i ], [ {{%.*}}, %if.else.i ]
+; CHECK: [[TOBOOL:%.*]] = icmp eq i64 [[PHIOFOPS]], 0
+;
+; CHECK-JT-LABEL: @testBI(
+; CHECK-JT: _ZL6calleei.exit.thread:
+;
+
+entry:
+ %call.i = call signext i32 @dummy(i32 signext %v)
+ %tobool.i = icmp eq i32 %call.i, 0
+ br i1 %tobool.i, label %if.else.i, label %if.then.i
+
+if.then.i: ; preds = %entry
+ %call2.i = call signext i32 @dummy(i32 signext %call.i)
+ %retval.sroa.22.0.insert.ext.i.i = zext i32 %call2.i to i64
+ %retval.sroa.22.0.insert.shift.i.i = shl nuw i64 %retval.sroa.22.0.insert.ext.i.i, 32
+ %retval.sroa.0.0.insert.insert.i.i = or i64 %retval.sroa.22.0.insert.shift.i.i, 1
+ br label %_ZL6calleei.exit
+
+if.else.i: ; preds = %entry
+ %.lobit.i = lshr i32 %v, 31
+ %0 = zext i32 %.lobit.i to i64
+ %retval.sroa.22.0.insert.ext.i8.i = zext i32 %v to i64
+ %retval.sroa.22.0.insert.shift.i9.i = shl nuw i64 %retval.sroa.22.0.insert.ext.i8.i, 32
+ %retval.sroa.0.0.insert.insert.i11.i = or i64 %retval.sroa.22.0.insert.shift.i9.i, %0
+ br label %_ZL6calleei.exit
+
+_ZL6calleei.exit: ; preds = %if.then.i, %if.else.i
+ %retval.sroa.0.0.i = phi i64 [ %retval.sroa.0.0.insert.insert.i.i, %if.then.i ], [ %retval.sroa.0.0.insert.insert.i11.i, %if.else.i ]
+ %rc.sroa.43.0.extract.shift = lshr i64 %retval.sroa.0.0.i, 32
+ %rc.sroa.43.0.extract.trunc = trunc i64 %rc.sroa.43.0.extract.shift to i32
+ %1 = and i64 %retval.sroa.0.0.i, 1
+ %tobool = icmp eq i64 %1, 0
+ br i1 %tobool, label %if.end, label %if.then
+
+if.then: ; preds = %_ZL6calleei.exit
+ %call1 = call signext i32 @dummy(i32 signext 0)
+ br label %if.end
+
+if.end: ; preds = %_ZL6calleei.exit, %if.then
+ ret i32 %rc.sroa.43.0.extract.trunc
+}
+
+
+define signext i32 @testIB(i32 signext %v) {
+; Test with std::pair<int, bool>
+; based on the following C++ code
+; std::pair<int, bool> callee(int v) {
+; int a = dummy(v);
+; if (a) return std::make_pair(dummy(v), true);
+; else return std::make_pair(v, v < 0);
+; }
+; int func(int v) {
+; std::pair<int, bool> rc = callee(v);
+; if (rc.second) dummy(0);
+; return rc.first;
+; }
+; CHECK-LABEL: @testIB(
+; CHECK: _ZL6calleei.exit:
+; CHECK: [[PHIOFOPS:%.*]] = phi i64 [ 4294967296, %if.then.i ], [ {{%.*}}, %if.else.i ]
+; CHECK: [[TOBOOL:%.*]] = icmp eq i64 [[PHIOFOPS]], 0
+;
+; CHECK-JT-LABEL: @testIB(
+; CHECK-JT: _ZL6calleei.exit.thread:
+;
+
+entry:
+ %call.i = call signext i32 @dummy(i32 signext %v)
+ %tobool.i = icmp eq i32 %call.i, 0
+ br i1 %tobool.i, label %if.else.i, label %if.then.i
+
+if.then.i: ; preds = %entry
+ %call1.i = call signext i32 @dummy(i32 signext %v)
+ %retval.sroa.0.0.insert.ext.i.i = zext i32 %call1.i to i64
+ %retval.sroa.0.0.insert.insert.i.i = or i64 %retval.sroa.0.0.insert.ext.i.i, 4294967296
+ br label %_ZL6calleei.exit
+
+if.else.i: ; preds = %entry
+ %.lobit.i = lshr i32 %v, 31
+ %0 = zext i32 %.lobit.i to i64
+ %retval.sroa.2.0.insert.shift.i8.i = shl nuw nsw i64 %0, 32
+ %retval.sroa.0.0.insert.ext.i9.i = zext i32 %v to i64
+ %retval.sroa.0.0.insert.insert.i10.i = or i64 %retval.sroa.2.0.insert.shift.i8.i, %retval.sroa.0.0.insert.ext.i9.i
+ br label %_ZL6calleei.exit
+
+_ZL6calleei.exit: ; preds = %if.then.i, %if.else.i
+ %retval.sroa.0.0.i = phi i64 [ %retval.sroa.0.0.insert.insert.i.i, %if.then.i ], [ %retval.sroa.0.0.insert.insert.i10.i, %if.else.i ]
+ %rc.sroa.0.0.extract.trunc = trunc i64 %retval.sroa.0.0.i to i32
+ %1 = and i64 %retval.sroa.0.0.i, 4294967296
+ %tobool = icmp eq i64 %1, 0
+ br i1 %tobool, label %if.end, label %if.then
+
+if.then: ; preds = %_ZL6calleei.exit
+ %call1 = call signext i32 @dummy(i32 signext 0)
+ br label %if.end
+
+if.end: ; preds = %_ZL6calleei.exit, %if.then
+ ret i32 %rc.sroa.0.0.extract.trunc
+}
+
+declare signext i32 @dummy(i32 signext %v)
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