[PATCH] D49448: [AMDGPU] Fix VGPR spills where offset doesn't fit in 12 bits

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added a comment.
This revision is now accepted and ready to land.

LGTM with the 2 remaining asms fixed



================
Comment at: test/CodeGen/AMDGPU/spill-offset-calculation.ll:75
+  ; Ensure the spill is of the full super-reg.
+  call void asm sideeffect "buffer_store_dwordx2 $0, off, s[0:3], s7", "r"(<2 x i32> %a)
+
----------------
Missed one


================
Comment at: test/CodeGen/AMDGPU/spill-offset-calculation.ll:106
+  ; Ensure the spill is of the full super-reg.
+  call void asm sideeffect "buffer_store_dwordx2 $0, off, s[0:3], s7", "r"(<2 x i32> %a)
+
----------------
Missed one


https://reviews.llvm.org/D49448