[llvm] r338011 - [AArch64][NFC] Removed tab characters from test files.

Sjoerd Meijer via llvm-commits llvm-commits at lists.llvm.org
Thu Jul 26 00:59:39 PDT 2018


Author: sjoerdmeijer
Date: Thu Jul 26 00:59:39 2018
New Revision: 338011

URL: http://llvm.org/viewvc/llvm-project?rev=338011&view=rev
Log:
[AArch64][NFC] Removed tab characters from test files.

Modified:
    llvm/trunk/test/MC/AArch64/directive-cpu.s
    llvm/trunk/test/MC/AArch64/neon-crypto.s

Modified: llvm/trunk/test/MC/AArch64/directive-cpu.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/directive-cpu.s?rev=338011&r1=338010&r2=338011&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/directive-cpu.s (original)
+++ llvm/trunk/test/MC/AArch64/directive-cpu.s Thu Jul 26 00:59:39 2018
@@ -1,47 +1,41 @@
 // RUN: llvm-mc -triple aarch64-unknown-none-eabi -filetype asm -o - %s 2>&1 | FileCheck %s
 
-	.cpu generic
+.cpu generic
+fminnm d0, d0, d1
+// CHECK: fminnm d0, d0, d1
+
+.cpu generic+fp
+fminnm d0, d0, d1
+// CHECK: fminnm d0, d0, d1
+
+.cpu generic+simd
+addp v0.4s, v0.4s, v0.4s
+// CHECK: addp v0.4s, v0.4s, v0.4s
+
+.cpu generic+crc
+crc32cx w0, w1, x3
+// CHECK: crc32cx w0, w1, x3
+
+.cpu generic+crypto+nocrc
+aesd v0.16b, v2.16b
+// CHECK: aesd v0.16b, v2.16b
 
-	fminnm d0, d0, d1
-
-	.cpu generic+fp
-
-	fminnm d0, d0, d1
-
-	.cpu generic+simd
-
-	addp v0.4s, v0.4s, v0.4s
-
-	.cpu generic+crc
-
-	crc32cx w0, w1, x3
-
-	.cpu generic+crypto+nocrc
-
-	aesd v0.16b, v2.16b
-
-	.cpu generic+lse
-  casa  w5, w7, [x20]
-
-// CHECK:	fminnm d0, d0, d1
-// CHECK:	fminnm d0, d0, d1
-// CHECK:	addp v0.4s, v0.4s, v0.4s
-// CHECK:	crc32cx w0, w1, x3
-// CHECK:	aesd v0.16b, v2.16b
+.cpu generic+lse
+casa  w5, w7, [x20]
 // CHECK: casa  w5, w7, [x20]
 
-  .cpu generic+aes
-  aese v0.16b, v1.16b
+.cpu generic+aes
+aese v0.16b, v1.16b
 // CHECK: aese  v0.16b, v1.16b
 
-  .cpu generic+sha2
-  sha1h s0, s1
+.cpu generic+sha2
+sha1h s0, s1
 // CHECK: sha1h s0, s1
 
-  .cpu generic+sha3
-  sha512h q0, q1, v2.2d
+.cpu generic+sha3
+sha512h q0, q1, v2.2d
 // CHECK: sha512h q0, q1, v2.2d
 
-  .cpu generic+sm4
-  sm4e v2.4s, v15.4s
+.cpu generic+sm4
+sm4e v2.4s, v15.4s
 // CHECK: sm4e  v2.4s, v15.4s

Modified: llvm/trunk/test/MC/AArch64/neon-crypto.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/neon-crypto.s?rev=338011&r1=338010&r2=338011&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/neon-crypto.s (original)
+++ llvm/trunk/test/MC/AArch64/neon-crypto.s Thu Jul 26 00:59:39 2018
@@ -14,18 +14,18 @@
 
 // CHECK-NO-CRYPTO: error: instruction requires a CPU feature not currently enabled
 // CHECK-NO-CRYPTO-ARM64: error: instruction requires: aes
-// CHECK: aese	v0.16b, v1.16b          // encoding: [0x20,0x48,0x28,0x4e]
-// CHECK: aesd	v0.16b, v1.16b          // encoding: [0x20,0x58,0x28,0x4e]
-// CHECK: aesmc	v0.16b, v1.16b          // encoding: [0x20,0x68,0x28,0x4e]
-// CHECK: aesimc	v0.16b, v1.16b        // encoding: [0x20,0x78,0x28,0x4e]
+// CHECK: aese v0.16b, v1.16b          // encoding: [0x20,0x48,0x28,0x4e]
+// CHECK: aesd v0.16b, v1.16b          // encoding: [0x20,0x58,0x28,0x4e]
+// CHECK: aesmc v0.16b, v1.16b         // encoding: [0x20,0x68,0x28,0x4e]
+// CHECK: aesimc v0.16b, v1.16b        // encoding: [0x20,0x78,0x28,0x4e]
 
         sha1h s0, s1
         sha1su1 v0.4s, v1.4s
         sha256su0 v0.4s, v1.4s
 
-// CHECK: sha1h	s0, s1                  // encoding: [0x20,0x08,0x28,0x5e]
-// CHECK: sha1su1	v0.4s, v1.4s          // encoding: [0x20,0x18,0x28,0x5e]
-// CHECK: sha256su0	v0.4s, v1.4s        // encoding: [0x20,0x28,0x28,0x5e]
+// CHECK: sha1h s0, s1                  // encoding: [0x20,0x08,0x28,0x5e]
+// CHECK: sha1su1 v0.4s, v1.4s          // encoding: [0x20,0x18,0x28,0x5e]
+// CHECK: sha256su0 v0.4s, v1.4s        // encoding: [0x20,0x28,0x28,0x5e]
 
         sha1c q0, s1, v2.4s
         sha1p q0, s1, v2.4s
@@ -35,10 +35,10 @@
         sha256h2 q0, q1, v2.4s
         sha256su1 v0.4s, v1.4s, v2.4s
 
-// CHECK: sha1c	q0, s1, v2.4s           // encoding: [0x20,0x00,0x02,0x5e]
-// CHECK: sha1p	q0, s1, v2.4s           // encoding: [0x20,0x10,0x02,0x5e]
-// CHECK: sha1m	q0, s1, v2.4s           // encoding: [0x20,0x20,0x02,0x5e]
-// CHECK: sha1su0	v0.4s, v1.4s, v2.4s   // encoding: [0x20,0x30,0x02,0x5e]
-// CHECK: sha256h	q0, q1, v2.4s         // encoding: [0x20,0x40,0x02,0x5e]
-// CHECK: sha256h2	q0, q1, v2.4s       // encoding: [0x20,0x50,0x02,0x5e]
-// CHECK: sha256su1	v0.4s, v1.4s, v2.4s // encoding: [0x20,0x60,0x02,0x5e]
+// CHECK: sha1c q0, s1, v2.4s           // encoding: [0x20,0x00,0x02,0x5e]
+// CHECK: sha1p q0, s1, v2.4s           // encoding: [0x20,0x10,0x02,0x5e]
+// CHECK: sha1m q0, s1, v2.4s           // encoding: [0x20,0x20,0x02,0x5e]
+// CHECK: sha1su0 v0.4s, v1.4s, v2.4s   // encoding: [0x20,0x30,0x02,0x5e]
+// CHECK: sha256h q0, q1, v2.4s         // encoding: [0x20,0x40,0x02,0x5e]
+// CHECK: sha256h2 q0, q1, v2.4s        // encoding: [0x20,0x50,0x02,0x5e]
+// CHECK: sha256su1 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x60,0x02,0x5e]




More information about the llvm-commits mailing list