[llvm] r337934 - [Hexagon] Properly scale bit index when extracting elements from vNi1

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed Jul 25 09:20:59 2018
New Revision: 337934

URL: http://llvm.org/viewvc/llvm-project?rev=337934&view=rev
Log:
[Hexagon] Properly scale bit index when extracting elements from vNi1

For example v = <2 x i1> is represented as bbbbaaaa in a predicate register,
where b = v[1], a = v[0]. Extracting v[1] is equivalent to extracting bit 4
from the predicate register.

Added:
    llvm/trunk/test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=337934&r1=337933&r2=337934&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Wed Jul 25 09:20:59 2018
@@ -2327,7 +2327,9 @@ HexagonTargetLowering::extractVector(SDV
     // If the value extracted is a single bit, use tstbit.
     if (ValWidth == 1) {
       SDValue A0 = getInstr(Hexagon::C2_tfrpr, dl, MVT::i32, {VecV}, DAG);
-      return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, IdxV);
+      SDValue M0 = DAG.getConstant(8 / VecWidth, dl, MVT::i32);
+      SDValue I0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV, M0);
+      return DAG.getNode(HexagonISD::TSTBIT, dl, MVT::i1, A0, I0);
     }
 
     // Each bool vector (v2i1, v4i1, v8i1) always occupies 8 bits in

Added: llvm/trunk/test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll?rev=337934&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/vect/extract-elt-vNi1.ll Wed Jul 25 09:20:59 2018
@@ -0,0 +1,18 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Make sure that element no.1 extracted from <2 x i1> translates to extracting
+; bit no.4 from the predicate register.
+
+; CHECK: p[[P0:[0-3]]] = vcmpw.eq(r1:0,r3:2)
+; CHECK: r[[R0:[0-9]+]] = p[[P0]]
+; This is what we're really testing: the bit index of 4.
+; CHECK: p[[P0]] = tstbit(r[[R0]],#4)
+
+define i32 @fred(<2 x i32> %a0, <2 x i32> %a1) #0 {
+  %v0 = icmp eq <2 x i32> %a0, %a1
+  %v1 = extractelement <2 x i1> %v0, i32 1
+  %v2 = zext i1 %v1 to i32
+  ret i32 %v2
+}
+
+attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }