[llvm] r337723 - [Hexagon] Handle unnamed globals in HexagonConstExpr

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Mon Jul 23 11:30:17 2018
New Revision: 337723

URL: http://llvm.org/viewvc/llvm-project?rev=337723&view=rev
Log:
[Hexagon] Handle unnamed globals in HexagonConstExpr

Instead of comparing names, compare positions in the parent module.

Added:
    llvm/trunk/test/CodeGen/Hexagon/cext-unnamed-global.mir
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonConstExtenders.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonConstExtenders.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonConstExtenders.cpp?rev=337723&r1=337722&r2=337723&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonConstExtenders.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonConstExtenders.cpp Mon Jul 23 11:30:17 2018
@@ -730,9 +730,21 @@ bool HCE::ExtRoot::operator< (const HCE:
     }
     case MachineOperand::MO_ExternalSymbol:
       return StringRef(V.SymbolName) < StringRef(ER.V.SymbolName);
-    case MachineOperand::MO_GlobalAddress:
-      assert(V.GV->hasName() && ER.V.GV->hasName());
-      return V.GV->getName() < ER.V.GV->getName();
+    case MachineOperand::MO_GlobalAddress: {
+      // Global values may not have names, so compare their positions
+      // in the parent module.
+      const Module &M = *V.GV->getParent();
+      auto FindPos = [&M] (const GlobalValue &V) {
+        unsigned P = 0;
+        for (const GlobalValue &T : M.global_values()) {
+          if (&T == &V)
+            return P;
+          P++;
+        }
+        llvm_unreachable("Global value not found in module");
+      };
+      return FindPos(*V.GV) < FindPos(*ER.V.GV);
+    }
     case MachineOperand::MO_BlockAddress: {
       const BasicBlock *ThisB = V.BA->getBasicBlock();
       const BasicBlock *OtherB = ER.V.BA->getBasicBlock();

Added: llvm/trunk/test/CodeGen/Hexagon/cext-unnamed-global.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/cext-unnamed-global.mir?rev=337723&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/cext-unnamed-global.mir (added)
+++ llvm/trunk/test/CodeGen/Hexagon/cext-unnamed-global.mir Mon Jul 23 11:30:17 2018
@@ -0,0 +1,38 @@
+# RUN: llc -march=hexagon -run-pass=hexagon-cext-opt %s -o - | FileCheck %s
+
+# Check that this test doesn't crash.
+# CHECK: %0:intregs = A2_tfrsi @0
+
+--- |
+  target triple = "hexagon"
+
+  @0 = external global [0 x i8]
+  @1 = external constant [2 x i64]
+
+  define void @f0() #0 {
+  b0:
+    tail call fastcc void @f1(float* inttoptr (i64 add (i64 ptrtoint ([0 x i8]* @0 to i64), i64 128) to float*), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @1, i32 0, i32 0))
+    ret void
+  }
+
+  declare fastcc void @f1(float* nocapture readonly, i64* nocapture readonly) #1
+
+  attributes #0 = { alwaysinline nounwind "target-cpu"="hexagonv60" }
+  attributes #1 = { noinline norecurse nounwind "target-cpu"="hexagonv60" }
+...
+
+---
+name: f0
+tracksRegLiveness: true
+body: |
+  bb.0:
+    %0:intregs = A2_tfrsi @0
+    %1:intregs = A2_tfrsi 0
+    %2:doubleregs = REG_SEQUENCE %0, %subreg.isub_lo, %1, %subreg.isub_hi
+    %3:doubleregs = CONST64 128
+    %4:doubleregs = A2_addp %2, %3
+    %5:intregs = A2_tfrsi @1
+    $r0 = COPY %4.isub_lo
+    $r1 = COPY %5
+    PS_tailcall_i @f1, hexagoncsr, implicit $r0, implicit $r1
+...