[PATCH] D49243: [X86] Improved sched models for X86 BT*rr instructions
Andrew V. Tischenko via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 23 04:08:01 PDT 2018
avt77 updated this revision to Diff 156741.
avt77 added a comment.
We decided that this patch won't include memory versions of instrs that's why I simply fixed tiny requirements like "place of WriteBitTest" and "removing of the TableGen CodeGenSchedule diffs".
https://reviews.llvm.org/D49243
Files:
lib/Target/X86/X86InstrInfo.td
lib/Target/X86/X86SchedBroadwell.td
lib/Target/X86/X86SchedHaswell.td
lib/Target/X86/X86SchedSandyBridge.td
lib/Target/X86/X86SchedSkylakeClient.td
lib/Target/X86/X86SchedSkylakeServer.td
lib/Target/X86/X86Schedule.td
lib/Target/X86/X86ScheduleAtom.td
lib/Target/X86/X86ScheduleBtVer2.td
lib/Target/X86/X86ScheduleSLM.td
lib/Target/X86/X86ScheduleZnver1.td
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