[llvm] r337651 - [SelectionDAGBuilder] Restrict vector reduction check to types with a power of 2 number of elements.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 21 22:16:49 PDT 2018
Author: ctopper
Date: Sat Jul 21 22:16:49 2018
New Revision: 337651
URL: http://llvm.org/viewvc/llvm-project?rev=337651&view=rev
Log:
[SelectionDAGBuilder] Restrict vector reduction check to types with a power of 2 number of elements.
The check for the shuffles usages probably isn't correct for non power of 2 vectors.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=337651&r1=337650&r2=337651&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Sat Jul 21 22:16:49 2018
@@ -2668,6 +2668,10 @@ static bool isVectorReductionOp(const Us
}
unsigned ElemNum = Inst->getType()->getVectorNumElements();
+ // Ensure the reduction size is a power of 2.
+ if (!isPowerOf2_32(ElemNum))
+ return false;
+
unsigned ElemNumToReduce = ElemNum;
// Do DFS search on the def-use chain from the given instruction. We only
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