[llvm] r337624 - [Hexagon] Disable packets in test to avoid ordering issues in checks

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Fri Jul 20 14:55:55 2018
New Revision: 337624

URL: http://llvm.org/viewvc/llvm-project?rev=337624&view=rev
Log:
[Hexagon] Disable packets in test to avoid ordering issues in checks

Modified:
    llvm/trunk/test/CodeGen/Hexagon/vec-call-full1.ll

Modified: llvm/trunk/test/CodeGen/Hexagon/vec-call-full1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/vec-call-full1.ll?rev=337624&r1=337623&r2=337624&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/vec-call-full1.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/vec-call-full1.ll Fri Jul 20 14:55:55 2018
@@ -1,4 +1,4 @@
-; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
+; RUN: llc -march=hexagon < %s | FileCheck %s
 
 ; CHECK-DAG: v{{[0-9]+}} = vmem(r{{[0-9]+}}+#0)
 ; CHECK-DAG: v{{[0-9]+}} = vmem(r{{[0-9]+}}+#0)
@@ -16,4 +16,4 @@ b0:
 
 declare void @f1(<32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>, <32 x i32>) #0
 
-attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b,-packets" }