[PATCH] D49574: [CodeGen] Fix ICE in SelectionDAG::computeKnownBits
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 20 10:58:58 PDT 2018
arsenm added a comment.
In https://reviews.llvm.org/D49574#1170008, @scott.linder wrote:
> Addressed feedback; updated other places where DemandedElts is zero extended to the source vector width.
>
> I do not have a FileCheck in the test because the passing condition is just for there to be no assert during CodeGen. There is nothing wrong with the IR/DAG/ISA at any point when the bug is or isn't present, so I don't know what to check for.
The operation ultimately produces something . In this case I would probably just use update_llc_checks
https://reviews.llvm.org/D49574
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