[PATCH] D49310: [llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms.

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb added inline comments.


================
Comment at: tools/llvm-mca/DispatchStage.cpp:110
   // An example of dependency-breaking instruction on X86 is a zero-idiom XOR.
-  if (!Desc.isZeroLatency())
-    for (std::unique_ptr<ReadState> &RS : IS.getUses())
----------------
lebedev.ri wrote:
> andreadb wrote:
> > andreadb wrote:
> > > lebedev.ri wrote:
> > > > andreadb wrote:
> > > > > lebedev.ri wrote:
> > > > > > So it will no longer even consider the sched profile?
> > > > > Not sure I understand the question. I am definitely using profile information from the scheduling model.
> > > > What i'm asking is - what happens if sched model says that instruction N has zero latency, but `isDependencyBreaking()` does not say that?
> > > In that case, instruction N will have to wait in the scheduler until input registers are all available. Then it is executed.
> > If it doesn’t work like that, then there is a bug. I cannot test it at the moment as I am not at work. I will check it on next days. Thanks.
> So the scheduler-profile-aware instruction scheduler will schedule it as-if it has zero latency,
> but the mca-based analysis will not?
> And how would one go about detecting such inconsistencies?
> This all makes me uneasy.
> 
No. I never said that.
It would still execute zero cycles. It simply has to wait for the operands.

Since I didn’t specifically test that bogus scenario, I will check that it really behaves like that. I cannot do that test  now because I am not at work. I will be back in a few days.



https://reviews.llvm.org/D49310