[PATCH] D49562: [X86][SSE] Use ISD::MULHU for constant/non-zero ISD::SRL lowering (PR38151)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon updated this revision to Diff 156458.
RKSimon added a comment.

Add partial support for shift-by-zero amounts - for v8i16 on SSE41+ targets where PBLENDW is available.


Repository:
  rL LLVM

https://reviews.llvm.org/D49562

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/combine-sdiv.ll
  test/CodeGen/X86/combine-shl.ll
  test/CodeGen/X86/vector-shift-lshr-128.ll
  test/CodeGen/X86/vector-shift-lshr-256.ll

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