[PATCH] D47681: [DAGCombiner] Bug 31275- Extract a shift from a constant mul or udiv if a rotate can be formed

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

Last-minute thought - should this be limited to some specific value types?
On X86, the RCL/RCR/ROL/ROR only exist for 8/16/32/64 bit widths. <http://felixcloutier.com/x86/RCL:RCR:ROL:ROR.html>


https://reviews.llvm.org/D47681