[PATCH] D49524: Avoid generating FGETSIGN for f16
Steve Canon via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 19 15:51:50 PDT 2018
This revision was automatically updated to reflect the committed changes.
Closed by commit rL337506: Skip out of SimplifyDemandedBits for BITCAST of f16 to i16 (authored by scanon, committed by ).
Changed prior to commit:
https://reviews.llvm.org/D49524?vs=156187&id=156380#toc
Repository:
rL LLVM
https://reviews.llvm.org/D49524
Files:
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/trunk/test/CodeGen/X86/pr38038.ll
Index: llvm/trunk/test/CodeGen/X86/pr38038.ll
===================================================================
--- llvm/trunk/test/CodeGen/X86/pr38038.ll
+++ llvm/trunk/test/CodeGen/X86/pr38038.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s
+; PR38038
+
+define i8 @crash(half) {
+entry:
+ %1 = bitcast half %0 to i16
+ %.lobit = lshr i16 %1, 15
+ %2 = trunc i16 %.lobit to i8
+ ret i8 %2
+}
Index: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1187,6 +1187,7 @@
bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, VT);
bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
if ((OpVTLegal || i32Legal) && VT.isSimple() &&
+ Op.getOperand(0).getValueType() != MVT::f16 &&
Op.getOperand(0).getValueType() != MVT::f128) {
// Cannot eliminate/lower SHL for f128 yet.
EVT Ty = OpVTLegal ? VT : MVT::i32;
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