[PATCH] D49248: [TargetLowering] Add support for non-uniform vectors to BuildUDIV

Simon Pilgrim via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jul 19 11:27:50 PDT 2018


RKSimon added inline comments.


================
Comment at: test/CodeGen/X86/combine-udiv.ll:383
+; SSE-NEXT:    movdqa %xmm0, %xmm1
+; SSE-NEXT:    psrlw $2, %xmm1
+; SSE-NEXT:    pblendw {{.*#+}} xmm1 = xmm0[0,1,2,3,4],xmm1[5,6],xmm0[7]
----------------
RKSimon wrote:
> efriedma wrote:
> > I guess it's sort of orthogonal to this patch, but this should probably be using pmulhuw for the shift.
> I raised this on PR38151 but haven't had time to get to it.
D49562 is an initial attempt at this.


Repository:
  rL LLVM

https://reviews.llvm.org/D49248





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