[PATCH] D49448: [AMDGPU] Fix VGPR spills where offset doesn't fit in 12 bits

[Scott Linder via Phabricator via llvm-commits]

scott.linder updated this revision to Diff 156306.
scott.linder added a comment.

Address some more feedback; use `-stress-regalloc` to cut down on the clobbers needed, add non-kernel tests, explicitly test the increment/decrement case, including the scratch offset SGPR.

I will try adding a MIR test to exercise the subregister condition and loop; with an IR test I don't know how to get a VGPR with subregs to survive "AMDGPU DAG->DAG Pattern Instruction Selection"


https://reviews.llvm.org/D49448

Files:
  lib/Target/AMDGPU/SIRegisterInfo.cpp
  test/CodeGen/AMDGPU/spill-offset-calculation.ll

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