[PATCH] D49436: [X86][BtVer2] correctly model the latency/throughput of LEA instructions.

[Phabricator via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL337469: [X86][BtVer2] correctly model the latency/throughput of LEA instructions. (authored by adibiagio, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D49436?vs=156249&id=156297#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D49436

Files:
  llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
  llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
  llvm/trunk/lib/Target/X86/X86.td
  llvm/trunk/lib/Target/X86/X86FixupLEAs.cpp
  llvm/trunk/lib/Target/X86/X86SchedPredicates.td
  llvm/trunk/lib/Target/X86/X86Schedule.td
  llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
  llvm/trunk/test/CodeGen/X86/lea32-schedule.ll
  llvm/trunk/test/CodeGen/X86/lea64-schedule.ll
  llvm/trunk/test/CodeGen/X86/mul-constant-i32.ll
  llvm/trunk/test/CodeGen/X86/mul-constant-i64.ll
  llvm/trunk/test/CodeGen/X86/schedule-x86-64-shld.ll
  llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-lea.s

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